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Extending The Benefits Of UVM To Include AMS: An Update On Accellera’s UVM-AMS Standard Development


By Tom Fitzpatrick and Peter Grove SoC teams can be divided up into design and verification groups. For digital designs, the Universal Verification Methodology (UVM), initially developed by Accellera and now standardized as IEEE 1800.2, has been the industry standard for the past decade. Since most SoC designs also have analog and mixed-signal IP blocks, it would be ideal for verification en... » read more

Updated UVM Cookbook Supports IEEE 1800.2 Standard And Emulation


I’m happy to announce that we at Mentor have just released a fully-updated version of our popular UVM Cookbook, which is available online here. Cookbook Overview Diagram The Universal Verification Methodology (UVM) is a standard library of SystemVerilog classes that supports a modular, reusable testbench architecture for constrained-random functional verification. Meanwhile, Mentor’... » read more

Best Practices


By Tom Fitzpatrick Active power control management for low-power designs has become a hot topic, especially with the latest update to the Unified Power Format standard. Version 2.1 was approved by IEEE on March 6, 2013. UPF gives the ability to specify power control for different parts of a design, separate from the RTL itself. The advent of low-power design has greatly increased the comple... » read more