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Extending The Benefits Of UVM To Include AMS: An Update On Accellera’s UVM-AMS Standard Development

Bringing reusable verification components and stimuli to analog and mixed-signal designs.

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By Tom Fitzpatrick and Peter Grove

SoC teams can be divided up into design and verification groups. For digital designs, the Universal Verification Methodology (UVM), initially developed by Accellera and now standardized as IEEE 1800.2, has been the industry standard for the past decade. Since most SoC designs also have analog and mixed-signal IP blocks, it would be ideal for verification engineers to be able to extend the UVM standard to handle Analog/Mixed-Signal (AMS) designs. Accellera has started a Working Group (WG) to create this new standard to benefit AMS designers. As the UVM-AMS standard is adopted by EDA vendors and IP providers, verification IP can be added into a testbench, raising the quality and productivity across chip projects. Reusing verification components and stimuli will boost productivity, and using UVM as a base allows verification engineers to branch into the mixed-signal space. Although the Accellera standard has been labelled UVM-AMS, its focus is on a methodology that will work whether the Device Under Test (DUT) is SPICE, RNM/DMS, or AMS.

AMS simulation involves either a co-simulation of digital-plus-analog solvers, or an event-driven solver for digital-plus-analog real number models.

A digital UVM example has a DUT connected to a UVM agent, also called a Universal Verification Component (UVC), using a virtual interface as shown below.

The UVC has several pieces, each with the following roles:

  • Sequencer – arbitrates between sequences of transactions
  • Driver – controls pins on the virtual interface (intf), based on transactions received from the sequencer
  • Monitor – reads responses from the DUT via the intf
  • Config – defines behaviors of the sequencer, driver, and monitor

Analog signals, such as sine waves, can be defined in the sequencer by just four values: frequency, phase, amplitude, and DC bias. The UVC for a mixed-signal environment needs to change the function of the driver so it no longer drives the DUT pins directly via the intf, but passes these sine wave properties to a physical module that then applies the stimulus to the DUT pin. This is a break from traditional UVM, but it is required when the DUT pin is mixed-signal. In UVM-AMS, the sequencer will still operate as before, but the driver now generates a request to the new physical module to implement the stimulus.

A more complex signal can be generated by combining an ideal sine wave along with a noise source, as shown below:

UVM-AMS proposes a Mixed-Signal (MS) Bridge module between the UVC and DUT in order to use continuously varying analog signals required by analog connections to the DUT. The MS bridge is a SystemVerilog (SV) wrapper module with a proxy API, SV interface, and analog resource module. The intf passes the digital and discrete signal values between the UVC and MS bridge. If you’re only driving real numbers, then just the intf is required. Continuous analog signals use the proxy where a request for the stimulus is made by the UVC driver and implemented using the analog resource. The analog resource can be a SystemVerilog or Verilog description if using RNM/DMS on a discrete DUT pin, or a Verilog-AMS description on a continuous electrical DUT pin. The implementation of how to drive out the sine wave is then part of this analog resource module. The example below shows the insertion of the MS bridge and proxy into the traditional UVM environment. The MS bridge SV wrapper serves two purposes: first, it enables SV constructs used by UVM to be used with the Verilog-AMS analog resource; and second, it enables the analog resource to be swapped for a different abstract view without having to change anything else.

When your testbench requires analog components (capacitor, resistor, inductor, diode, current source, voltage source), you can specify that as Verilog-AMS code in the analog resource, and the components will be controlled by proxy. Here’s an example for setting and getting a capacitance value showing a proxy template API, a proxy instance in the MS bridge module, and a UVM config setting:

The standard proposes four methods to interact with the Verilog-AMS resource, three of which are shown below. The missing one is a way to push the request to change the value but block the return until this change has completed. Within Verilog-AMS, values change from one value to another using a ramp rather than a step change.

Doubler switch example

Consider the example of a doubler switch in UVM-AMS using real number modeling (RNM) in our DUT, where only a virtual interface (intf) is required and no proxy. We are driving two inputs (IN, CK) and monitoring one output (OUT).

The SystemVerilog code of the DUT using real number modeling is written as:

An alternative way to model the same doubler switch in the DUT is by using Verilog-AMS or SPICE; the analog resource in our MS bridge then adds Connect Modules (CM) to interface between analog and digital domains. While this appears the neatest solution, the connect modules now control the transition changes in the value from the intf to the DUT pins, which can’t be controlled by the UVC. In addition, if some pins are current and others voltage (or a mix of the two), then the configuration of the connect modules becomes problematic. For some use cases this might be good enough.

The Verilog-AMS code of the DUT for the doubler switch has the following syntax:

A third option for the doubler switch is adding a proxy to the MS bridge to control the conversion between digital and electrical, while the UVC remains unchanged. Here the analog resource is a custom written module, which via the proxy allows full control of the D2A/A2D boundary.

It’s a best practice when writing code in your analog resource to also use UVM messaging to report information, warnings, errors, and fatal conditions for developers and users of UVM-AMS. The UVM package can’t be imported into a Verilog-AMS module directly, but by using upscoping and the SystemVerilog wrapper (MS bridge), it is possible. This exposes the analog resource to the full potential of the UVM messaging system.

Motivation for UVM-AMS

The planned UVM-AMS standard will encourage support by EDA and IP providers, so they can offer pre-built AMS Verification IP that can be easily integrated into a UVM-AMS testbench. Productivity and quality of AMS verification are the big benefits across new projects through the reuse of proven verification components and stimuli. The UVM-AMS WG is only focused on standards and showing others examples of how to write their own verification IP. In summary, the WG will provide examples of the interactions between the analog and digital engines via the analog resource, as well as the code required to support UVM messaging from a Verilog-AMS module.

UVM has provided our industry great productivity and reuse benefits for digital designs, and the plan is that UVM-AMS will extend those benefits to include a standardized AMS methodology that can scale, is reusable, and promotes metric-driven, mixed-signal verification. During the proposal phase, the design and verification community is invited to influence the specification of UVM-AMS by participating in the working group.

Peter Grove is SystemVerilog AMS Working Group Chair and member of the UVM-AMS Working Group at Accellera. He holds MS degrees in Engineering/Electronics from the University of Edinburgh.



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