tag: verification IP

AI Won’t Kill Verification IP, But It Will Redefine It
By Ann Mutschler - 26 Mar, 2026 - Comments: 0

Key Takeaways AI will enhance, not replace, verification IP by automating test generation and debug. Verification IP’s core value will increasingly lie in trust, accountability, and system-level realism, especially as designs become more complex, multi-die, and security-sensitive. AI shifts verification bottlenecks from execution to specification quality, raising expectations for c... » read more

Verifying Scale-Up And Scale-Out In Data Centers
By Ed Sperling - 26 Feb, 2026 - Comments: 0

Semiconductor Engineering sat down to discuss challenges and solutions for data center build-out and build-up with Gordon Allan, Siemens EDA director of verification IP; Rishi Chugh, vice president of product marketing for network switching at Marvell; Saravanan Kalinagasamy, senior director of ASIC design and validation at Astera Labs; and Jalaj Gupta, product engineering lead at Siemens EDA. ... » read more

Arm Performance Cookbook: Your Guide to Optimal Design and Verification (EBook)
By Cadence - 10 Dec, 2025 - Comments: 0

The Performance Cookbook for Arm is your essential resource for mastering the complexities of system-level performance, architecture exploration, and SoC verification. Why Download the Performance Cookbook? In-Depth Exploration - Dive into the evolution of Arm compute subsystem architectures, with detailed coverage on how critical components interact to deliver optimal performance be... » read more

PCIe Low-Power Validation Challenges And Potential Solutions
By Kunal Chhabriya - 13 Nov, 2025 - Comments: 0

As chip complexities increase and the industry evolves to more battery-powered devices, power-aware/consumption research becomes an integral part of design in the industry. Low power is crucial in ASIC applications to ensure longevity, durability, and reliability. PCI-SIG has focused on reducing power consumption while the PCIe interface is active to enable better platform power management (... » read more

Questa One Avery VIP: Accelerated Confidence In Complex Protocol Verification
By Siemens EDA - 21 Jul, 2025 - Comments: 0

In today’s rapidly advancing digital landscape, the role of functional verification has never been more critical. As systems become increasingly complex, ensuring their reliability and performance poses significant challenges for both design and verification engineers. The stakes are high; verification failures can lead to costly recalls, safety risks, and damage to brand reputation. The late... » read more

Averting Hacks Of PCIe Transport Using CMA/SPDM
By Siemens EDA - 09 Jan, 2025 - Comments: 0

This paper describes the component measurement and authentication (CMA) and security protocol and data model (SPDM) flow used to establish the secure channels required for the transmission of encrypted packets. The various approaches, namely the symmetric and asymmetric flows, will be discussed in establishing a secure connection with the implementation of CMA/SPDM packets through data objects.... » read more

Harnessing Computational Storage For Faster Data Processing
By Ujjwal Negi - 14 Nov, 2024 - Comments: 0

By Ujjwal Negi and Prashant Dixit In the evolving landscape of data storage, computational storage devices (CSDs) are revolutionizing how we process and store data. By embedding processing capabilities within storage units, these devices enable in-situ data manipulation, minimizing data movement between storage and CPUs and dramatically improving performance and efficiency. This paradigm shi... » read more

Accelerating Verification Of Computational Storage Designs Using Avery NVMe Verification IP
By Siemens EDA - 14 Nov, 2024 - Comments: 0

Computational storage is an emerging paradigm that integrates processing capabilities directly within storage devices. This paper outlines how this approach addresses the limitations of traditional NVM Express (NVMe) SSDs and the performance characteristics of the newly introduced compute and subsystem local memory (SLM) namespaces. The paper also focuses on the verification framework provided ... » read more

Partial Header Encryption In Integrity And Data Encryption For PCIe
By Kunal Chhabriya - 10 Oct, 2024 - Comments: 0

Partial Header Encryption (PHE) is an additional mechanism added to Integrity and Data Encryption (IDE) in PCIe 6.0 to prevent side-channel attacks based on attacker analysis of the information included in the headers. This blog narrates PHE flow and Cadence VIP support for PHE in IDE across PCIe/CXL protocols. Background Introducing PCIe's Integrity and Data Encryption Feature is an excell... » read more

DDR5 UDIMM Evolution To Clock Buffered DIMMs (CUDIMM)
By Shyam Sharma - 26 Sep, 2024 - Comments: 0

DDR5 is the latest generation of PCDDR memory that is used in a wide range of application like data centers, Laptops and personal computers, autonomous driving systems, servers, cloud computing, and gaming are now increasingly being used for AI applications with advances in memory bandwidth and density to allow DDR5 DIMMs (Dual Inline Memory Modules) to support densities higher then 256 GB per ... » read more

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