The evolution of RISC-V processor verification methodology using COREV-VERIF as a case study.
The OpenHW Group’s [1] Verification task group has been a pioneer in the development of methodologies and verification collateral for RISC-V processor verification. Since 2019 the members have worked together to develop CORE-V-VERIF: a UVM environment for the verification of RISC-V processor cores. Over this period of time the CORE-V-VERIF environment has evolved as new processor verification projects introduced new challenges, and learnings from the previous projects led to the development of new approaches. With each generation the CORE-V-VERIF environment has improved to become more robust, more reusable, and ultimately better at finding RTL bugs. The current generation uses RISC-V processor verification IP enabled by the open standard RISC-V Verification Interface (RVVI) [2] to realize a comprehensive verification methodology that encompasses asynchronous peripheral events that occur randomly during program execution. This paper will describe the evolution of RISC-V processor verification methodology using COREV-VERIF as a case study. Readers will learn a proven approach to RISC-V processor verification that can be accessed through an open-source example.
By Lee Moore, Imperas Software, Aimee Sutton, Imperas Software, Mike Thompson, OpenHW Group.
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