中文 English

RISC-V Processor Verification: Case Study


Abstract: The open RISC-V instruction set architecture is gaining traction with both semiconductor vendors and systems companies. A key question is how to verify the RISC-V processor implementation, especially when developing the RTL and/or adding custom instructions? This paper reports on the techniques used and lessons learned for the verification of a RV64IMACBNSU RISC-V processor by an exp... » read more

A Methodology To Verify Functionality, Security, And Trust for RISC-V Cores


Modern processor designs present some of the toughest hardware verification challenges. These challenges are especially acute for RISC-V processor core designs, with a wide range of variations and implementations available from a plethora of sources. This paper describes a verification methodology available to both RISC-V core providers and system-on-chip (SoC) teams integrating these cores. It... » read more

Verifying PULPino RISCY Core For A Google Accelerator With STING


Authors: Shubhodeep Roy Choudhury1, Shajid Thiruvathodi2, Vaidyanathan Seetharaman3, Matt Cockrell4, Jon Michelson5, Jason Redgrave6 Valtrix Technologies Private Limited, Bangalore, INDIA1, 2 Google Inc., Mountain View, USA3,4,5,6 Abstract: — Google uses the PULPino RISC-V core RISCY as a job scheduling and dispatch mechanism for a hardware accelerator (similar to a GPU controller). This... » read more