A verification method for RISC-V core providers and system-on-chip (SoC) teams integrating these cores.
Modern processor designs present some of the toughest hardware verification challenges. These challenges are especially acute for RISC-V processor core designs, with a wide range of variations and implementations available from a plethora of sources. This paper describes a verification methodology available to both RISC-V core providers and system-on-chip (SoC) teams integrating these cores. It spans functional correctness, including compliance, detection of security vulnerabilities, and trust verification that no malicious logic has been inserted. Detailed examples of design bugs found in actual RISC-V core implementations are included.
Authors:
W. W. Chen, OneSpin Solutions, Munich, Germany
N. Tusinschi, OneSpin Solutions, Munich, Germany
T. L. Anderson, OneSpin Solutions, San Jose, CA, USA
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