The Role Of EDA In AI


Semiconductor Engineering sat down to discuss the role that EDA has in automating artificial intelligence and machine learning with Doug Letcher, president and CEO of Metrics; Daniel Hansson, CEO of Verifyter; Harry Foster, chief scientist verification for Mentor, a Siemens Business; Larry Melling, product management director for Cadence; Manish Pandey, Synopsys fellow; and Raik Brinkmann, CEO ... » read more

The Weather Report: 2018 Study On IC/ASIC Verification Trends


Nobel Laureate Bob Dylan observed, “You don’t need a weatherman to know which way the wind blows.” Similarly, we can get a feeling for where our industry is going by attending to the flow of thought at conferences, on line, or in our daily business. But that gives us only a small window to observe the hurricane-like forces of the very large and complicated, extremely dynamic global semico... » read more

ANSYS 5G SoC Solutions


System-On-Chips for 5G smartphones and networks are complicated since they need to manage huge amounts of antenna data and offer significantly high processing capabilities in a power and thermally constrained environments. ANSYS tools provide thermal, reliability, power-timing and electromagnetic analyses of SoCs that can reveal design weaknesses and prevent system failures. Multiphysics soluti... » read more

Big Shift In Multi-Core Design


Hardware and software engineers have a long history of working independently of each other, but that insular behavior is changing in emerging areas such as AI, machine learning and automotive as the emphasis shifts to the system level. As these new markets consume more semiconductor content, they are having a big impact on the overall design process. The starting point in many of these desig... » read more

Digital Twins Deciphered


Ever since Siemens acquired Mentor Graphics in 2016, a new phrase has become more common in the semiconductor industry – the digital twin. Exactly what that is, and what impact it will have on the semiconductor industry, is less clear. In fact, many in the industry are scratching their heads over the term. The initial reaction is that the industry has been creating what are now termed digi... » read more

When Correct Is Not Enough: Formal Verification of Fault-Tolerant Hardware


Once upon a time, hardware functional verification was all about ensuring that a circuit would perform its specified functions under all legal input stimuli. Today, though, gaining confidence that a hardware design is correct is often not enough. Several industries, including automotive, medical, and aerospace, rely on safety-critical hardware to keep people safe. Other systems, for example, in... » read more

Accelerating Toshiba’s SoC Design with Fusion Compiler


This white paper discusses how Toshiba and Synopsys worked closely to bring-up Fusion Compiler and deploy it throughout Toshiba's advanced proprietary Tachyon Design System. With improved power, performance, and area (PPA), faster time-to-results and a predictable design flow have been validated on the latest, differentiated automotive SoC ASIC products, and Fusion Compiler is being broadly dep... » read more

Chips That See


An opto-based microchip implemented in standard CMOS technology has made it possible to develop a new type of on-chip functionality which combines normal ASIC technology with optical filters on the chip diode. The chip emulates the human eye and the way it detects light can be used for industrial purposes to create artificial intelligence for functions such as 3D motion control, eye protection ... » read more

The Challenge Of RISC-V Compliance


The open-source RISC-V instruction set architecture (ISA) continues to gain momentum, but the flexibility of RISC-V creates a problem—how do you know if a RISC-V implementation fits basic standards and can play well with other implementations so they all can run the same ecosystem? In addition, how do you ensure that ecosystem development works for all implementations and that all cores that ... » read more

Can Debug Be Tamed?


Debug consumes more time than any other aspect of the chip design and verification process, and it adds uncertainty and risk to semiconductor development because there are always lingering questions about whether enough bugs were caught in the allotted amount of time. Recent figures suggest that the problem is getting worse, too, as complexity and demand for reliability continue to rise. The... » read more

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