Author's Latest Posts

Embedded FPGA Basics

You do not need know about FPGAs to integrate reconfigurable RTL into your SoC: our software maps your RTL into our EFLX array for you.  But if you are curious, read on. FPGAs are field programmable gate arrays. They offer a different kind of programmability from processors.  Processors are sequential while FPGAs enable massive parallelism.  A processor has one adder, one multiplier—an ... » read more

Overview of NMAX Neural Inferencing

At HotChips 2018, Microsoft presented the attached slide in their Brainwave presentation: the ideal is to achieve high hardware utilization at low batch size. Existing architectures don’t do this: they have high utilization only at high batch sizes which means high latency. NMAX’ architecture loads weights quickly achieving almost the same high utilization at batch=1 as at large batch sizes... » read more

Performance Benchmarking Embedded FPGAs

When evaluating the performance of an embedded FPGA, one needs to evaluate the performance of each of the individual modules that make up an FPGA. The basic modules are: Reconfigurable logic building blocks (RBB-Logic), Fine-granularity logic containing LUTs, carry-forwarding adder chain, and flip-flops Reconfigurable DSP building blocks (RBB-DSP), Medium-granularity arith... » read more

Tiling Is Critical For eFPGA Users: ArrayLinx Delivers

FPGA chips come in multiple sizes — modular blocks of programmable logic, DSP MACs and RAM are intermixed in different sizes and ratios then stitched together with top-level interconnect, clocking, etc and surrounded by a ring of I/Os like GPIO, SerDes, USB, etc. There is extensive engineering and top-level physical design for each distinct FPGA array and chip. eFPGA is different: Custome... » read more

SM2: A Deep Neural Network Accelerator In 28nm

Deep learning algorithms present an exciting opportunity for efficient VLSI implementations due to several useful properties: (1) an embarrassingly parallel dataflow graph, (2) significant sparsity in model parameters and intermediate results, and (3) resilience to noisy computation and storage. Exploiting these characteristics can offer significantly improved performance and energy efficiency.... » read more

eFPGA IP Density, Portability And Scalability

FPGA chip companies generally build a new generation of FPGAs every ~3 years when there is a major advance in process technology. They pick one foundry, one node, one variation of that node and do full-custom circuit design with typically the maximum or near-maximum number of metal layers in order to get the highest density FPGA they can. It takes them most of the 3 years to do the complex e... » read more