Resilient And Secure Programmable SoC Accelerator Offload (KAUST)


A technical paper titled “Resilient and Secure Programmable System-on-Chip Accelerator Offload” was published by researchers at King Abdullah University of Science and Technology (KAUST).


“Computational offload to hardware accelerators is gaining traction due to increasing computational demands and efficiency challenges. Programmable hardware, like FPGAs, offers a promising platform in rapidly evolving application areas, with the benefits of hardware acceleration and software programmability. Unfortunately, such systems composed of multiple hardware components must consider integrity in the case of malicious components. In this work, we propose Samsara, the first secure and resilient platform that derives, from Byzantine Fault Tolerant (BFT), protocols to enhance the computing resilience of programmable hardware. Samsara uses a novel lightweight hardware-based BFT protocol for Systems-on-Chip, called H-Quorum, that implements the theoretical-minimum latency between applications and replicated compute nodes. To withstand malicious behaviors, Samsara supports hardware rejuvenation, which is used to replace, relocate, or diversify faulty compute nodes. Samsara’s architecture ensures the security of the entire workflow while keeping the latency overhead, of both computation and rejuvenation, close to the non-replicated counterpart.”

Find the technical paper here. Published June 2024 (preprint).

Gouveia, Inês Pinto, Ahmad T. Sheikh, Ali Shoker, Suhaib A. Fahmy, and Paulo Esteves-Verissimo. “Resilient and Secure Programmable System-on-Chip Accelerator Offload.” arXiv preprint arXiv:2406.18117 (2024).

Related Reading
Security Focus Widens To HW, SW, Ecosystems
Change reflects higher value of data and push to more heterogeneous designs.
Why It’s So Hard To Secure AI Chips
Much of the hardware is the same, but AI systems have unique vulnerabilities that require novel defense strategies.

Leave a Reply

(Note: This name will be displayed publicly)