中文 English

Cybersecurity & FPGA Devices


A technical paper titled "A Survey on FPGA Cybersecurity Design Strategies" is presented by researchers at Université Laval, Canada. Abstract (partial): "This paper presents a critical literature review on the security aspects of field programmable gate array (FPGA) devices. FPGA devices present unique challenges to cybersecurity through their reconfigurable nature. This paper also pays sp... » read more

Using eFPGAs For Security


Andy Jaros, vice president at Flex Logix, talks about the use of eFPGAs to keep pace with security risks over longer chip lifetimes, how configurable RTL can help, and why systems companies are altering the playing field for FPGAs. » read more

Implementations of 2D Material-Based Devices For IoT Security


A new research paper titled "Application of 2D Materials in Hardware Security for Internet-of-Things: Progress and Perspective" was published by researchers at National University of Singapore and A*STAR. The paper explores the "implementation of hardware security using 2D materials, for example, true random number generators (TRNGs), physical unclonable functions (PUFs), camouflage, and ant... » read more

Hardware Implementation Of A Random Gumber Generator On A FPGA


A new research paper titled "FPGA Random Number Generator" was published by a researcher at Johns Hopkins University. According to the paper's abstract: "This paper offers a proof-of-concept for creating a verilog-based hardware design that utilizes random measurement and scrambling algorithms to generate 32-bit random synchronously with a single clock cycle on a field-programmable-gate-arr... » read more

New Processor Fuzzing Mechanism


Researchers from Boston University and University of Washington published a technical paper titled "ProcessorFuzz: Guiding Processor Fuzzing using Control and Status Registers." Abstract "As the complexity of modern processors has increased over the years, developing effective verification strategies to identify bugs prior to manufacturing has become critical. Undiscovered micro-architectur... » read more

Evaluation of Automotive HW Trust Anchors Regarding Their Feasibility In Vehicle Architectures


A new technical paper titled "Analysis and Evaluation of Hardware Trust Anchors in the Automotive Domain" was published by researchers at Fraunhofer Institute SIT and CARIAD. Abstract "Automotive architectures get increasingly more complex both regarding internal as well as external connections to offer new services like autonomous driving. This development further broadens the cyberattack ... » read more

Vulnerability of Neural Networks Deployed As Black Boxes Across Accelerated HW Through Electromagnetic Side Channels


This technical paper titled "Can one hear the shape of a neural network?: Snooping the GPU via Magnetic Side Channel" was presented by researchers at Columbia University, Adobe Research and University of Toronto at the 31st USENIX Security Symposium in August 2022. Abstract: "Neural network applications have become popular in both enterprise and personal settings. Network solutions are tune... » read more

Design For Security Now Essential For Chips, Systems


It's nearly impossible to create a completely secure chip or system, but much can be done to raise the level of confidence about that security. In the past, security was something of an afterthought, disconnected from the architecture and added late in the design cycle. But as chips are used increasingly in safety- and mission-critical systems, and as the value of data continues to rise, the... » read more

ML-Based Framework for Automatically Generating Hardware Trojan Benchmarks


A new technical paper titled "Automatic Hardware Trojan Insertion using Machine Learning" was published by researchers at University of Florida and Stanford University. Abstract (partial): "In this paper, we present MIMIC, a novel AI-guided framework for automatic Trojan insertion, which can create a large population of valid Trojans for a given design by mimicking the properties of a small... » read more

Formal Verification Methodology For Detecting Security-Critical Bugs in HW & in the HW/Firmware Interface of SoCs (Award Winner)


A new technical paper titled "A Formal Approach to Confidentiality Verification in SoCs at the Register Transfer Level" was this year's first place winner of Intel's Hardware Security Academic Award program.   The approach utilizes UPEC (Unique Program Execution Checking) to identify functional design bugs causing confidentiality violations, covering both the processor and its peripherals. ... » read more

← Older posts