tag: hardware security

The One Bit Problem That Can Break a System
By Ann Mutschler - 02 Apr, 2026 - Comments: 2

Key Takeaways: Bit flipping is no longer a rare reliability issue but a systemic risk driven by shrinking process nodes, higher clock speeds, lower voltages, and radiation exposure, leading to silent data corruption and potential system failure. The same mechanisms that cause accidental bit flips can be deliberately exploited through techniques such as clock, voltage, laser, and rowhamm... » read more

Secure at First Silicon: Reducing Cost and Risk
By Keysight - 01 Apr, 2026 - Comments: 0

Security weaknesses related to side-channel leakage are often discovered far too late in the lifecycle of a chip. Design teams may focus on functionality, performance, and power, assuming that a robust algorithm like AES is enough to guarantee security. Only after first silicon comes back – and an expert lab starts probing power traces or EM emissions – do they realize that sensitive inform... » read more

Hardware Deployment for Secure AI Using Confidential Computing
By Rambus - 01 Apr, 2026 - Comments: 0

AI’s fast evolution is producing autonomous systems that can operate with minimal human oversight, improve themselves and become effective at decision-making in complex environments. These developments require careful consideration of security and privacy. To limit the overhead performance impact (area, throughput, latency and power), hardware-based security solutions can be deploye... » read more

In-Depth Analysis of 187 Publications on Hardware Reverse Engineering (Ruhr U., MPI)
By Technical Paper Link - 27 Mar, 2026 - Comments: 0

A new technical paper, "SoK: From Silicon to Netlist and Beyond Two Decades of Hardware Reverse Engineering Research," was published by the Ruhr University Bochum and the Max Planck Institute for Security and Privacy. Abstract "As hardware serves as the root of trust in modern computing systems, Hardware Reverse Engineering (HRE) is foundational for security assurance. In practice, HRE en... » read more

How SW and HW Vulnerabilities Can Complement LLM-Specific Algorithmic Attacks (UT Austin, Intel et al.)
By Technical Paper Link - 20 Mar, 2026 - Comments: 0

A new technical paper, "Cascade: Composing Software-Hardware Attack Gadgets for Adversarial Threat Amplification in Compound AI Systems," was published by the University of Texas, Austin, Intel Labs, Symmetry Systems, Microsoft and Georgia Tech. Abstract "Rapid progress in generative AI has given rise to Compound AI systems - pipelines comprised of multiple large language models (LLM), so... » read more

Identifying Read Disturbance Threshold of DRAM Chips (ETH Zurich, Rutgers)
By Technical Paper Link - 17 Mar, 2026 - Comments: 0

A new technical paper, "DiscoRD: An Experimental Methodology for Quickly Discovering the Reliable Read Disturbance Threshold of Real DRAM Chips," was published by ETH Zurich and Rutgers University. Abstract "State-of-the-art DRAM read disturbance mitigations rely on the read disturbance threshold (RDT) (e.g., the number of aggressor row activations needed to induce the first read disturba... » read more

Electrical Model of the Bitflip in SRAM Under Laser Illumination Simulating Laser Fault Injection
By Technical Paper Link - 22 Feb, 2026 - Comments: 0

A new technical paper, "Electrical modelisation of a bitflip in SRAM cell memory induced by laser fault injection," was published by researchers at Univ Rennes, CNRS, IETR. Abstract "An electrical model of the bitflip in SRAM under laser illumination simulating laser fault injection is proposed. This model is based on a bipolar phototransistor responsible of the amplified induced photocur... » read more

Information Flow Verification Framework Integrating Static and Formal Verification Methods At The Pre-Silicon Stage (U. of Florida)
By Technical Paper Link - 10 Feb, 2026 - Comments: 0

Researchers from University of Florida published "IFV: Information Flow Verification at the Pre-silicon Stage Utilizing Static-Formal Methodology." Abstract "Modern system-on-chips (SoCs) are becoming prone to numerous security vulnerabilities due to their ever-growing complexity and size. Therefore, a comprehensive security verification framework is needed at the very early stage of the ... » read more

HW-Triggered Backdoors Across Common GPU Accelerators (BIFOLD, TU Berlin, CISPA)
By Technical Paper Link - 02 Feb, 2026 - Comments: 0

A new technical paper titled "Hardware-Triggered Backdoors" was published by researchers at Berlin Institute for the Foundations of Learning and Data (BIFOLD), TU Berlin and CISPA Helmholtz Center for Information Security. Abstract "Machine learning models are routinely deployed on a wide range of computing hardware. Although such hardware is typically expected to produce identical result... » read more

Chip Industry Week In Review
By The SE Staff - 30 Jan, 2026 - Comments: 0

Big deals and fundings Teradyne and MultiLane are forming a joint venture, MultiLane Test Products (MLTP), to accelerate the development of test solutions for high speed data connections.  Teradyne will be the majority owner. Ricursive Intelligence raised $300M Series A for AI-driven IC design. IonQ plans to acquire SkyWater for ~$1.8B, creating a "vertically integrated full-stack q... » read more

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