Performant Side-Channel Resistant RISC-V Core to Secure Neural Network Inference (Northeastern Univ.)


A new technical paper titled "PermuteV: A Performant Side-channel-Resistant RISC-V Core Securing Edge AI Inference" was published by researchers at Northeastern University. Abstract "Edge AI inference is becoming prevalent thanks to the emergence of small yet high-performance microprocessors. This shift from cloud to edge processing brings several benefits in terms of energy savings, impr... » read more

Chip Industry Week in Review


SIA's latest monthly global semiconductor sales report reflects a ~30% YOY increase, hitting a record $75.3B in November 2025. Asia Pacific had a notable 66% increase. Cadence launched its Chiplet Spec-to-Packaged Parts ecosystem to accelerate time to market for chiplet development for physical AI, data centers, and HPC applications. Initial IP partners joining Cadence include Arm, Arteris, ... » read more

Is End-To-End Security Possible?


Looming financial penalties for data breaches are forcing chipmakers to confront end-to-end security, an increasingly complex and daunting problem because no single company controls all the pieces anymore. This is especially apparent in multi-die assemblies, in use today in data centers, and under consideration in automotive and other applications. Multiple chiplets can push performance well... » read more

Five Tips To Avoid Security Errors In Product Development


Riscure, now part of Keysight, has been helping chip vendors and device manufacturers improve the security of their products for years. The security scenario has changed a lot over time. The attacker profile evolved from individuals motivated by curiosity, with very limited resources and attack potential, to well-funded and organized adversaries with malicious motivations and the capacity to ex... » read more

The Evolution Of Hardware Root Of Trust Security IP


Navigate hardware-based security for semiconductors with this white paper about tRoot Hardware Secure Modules (HSMs). This paper provides security solutions for protecting digital assets in an increasingly interconnected world. Key Takeaways: Understand why robust security measures are needed for AI, IoT, and high-performance computing. Discover tRoot HSMs features, including secure ... » read more

A Review Of Acoustic Side-Channel Attacks: An AI View (Penn State Univ.)


A new technical paper titled "A Survey on Acoustic Side-Channel Attacks: An Artificial Intelligence Perspective" was published by researchers at Penn State University. Abstract "Acoustic Side-Channel Attacks (ASCAs) exploit the sound produced by keyboards and other devices to infer sensitive information without breaching software or network defenses. Recent advances in deep learning, large ... » read more

Two-Stage Hardware Fuzzer (TU Darmstadt)


A new technical paper titled "GoldenFuzz: Generative Golden Reference Hardware Fuzzing" was published by researchers at TU Darmstadt. Abstract "Modern hardware systems, driven by demands for high performance and application-specific functionality, have grown increasingly complex, introducing large surfaces for bugs and security-critical vulnerabilities. Fuzzing has emerged as a scalable sol... » read more

Analysis of EM Side Channel Attacks On Smartphones (Fraunhofer AISEC, BSI, TUM)


A new technical paper titled "Breaking ECDSA with Electromagnetic Side-Channel Attacks: Challenges and Practicality on Modern Smartphones" was published by researchers at Fraunhofer Institute for Applied and Integrated Security (AISEC), German Federal Office for Information Security, and TU Munich. Abstract "Smartphones handle sensitive tasks such as messaging and payment and may soon sup... » read more

Adaptive Fuzzing Framework that Reuses Tests from Prior Processors (Texas A&M, TU Darmstadt)


A new technical paper titled "ReFuzz: Reusing Tests for Processor Fuzzing with Contextual Bandits" was published by researchers at Texas A&M University and TU Darmstadt. Abstract "Processor designs rely on iterative modifications and reuse well-established designs. However, this reuse of prior designs also leads to similar vulnerabilities across multiple processors. As processors grow... » read more

HW Security: Inner Product Masking With Fault Detection Via ISE (KU Leuven, NUS, Rambus)


A new technical paper titled "Extending and Accelerating Inner Product Masking with Fault Detection via Instruction Set Extension" was published by researchers at KU Leuven, National University of Singapore, and Rambus. Abstract  "Inner product masking is a well-studied masking countermeasure against side-channel attacks. IPM-FD further extends the IPM scheme with fault detection capabil... » read more

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