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Hardware Root of Trust: Everything You Need To Know


As explained in our “Secure Silicon IP Webinar Series“, a root of trust is the security foundation for an SoC, other semiconductor device or electronic system. However, its meaning differs depending on who you ask. For example, the hardware root of trust contains the keys for cryptographic functions and is usually a part of the secure boot process providing the foundation for the software c... » read more

Anti-Tamper Benefits Of Encrypted Helper-Data Images For PUFs


PUFs are mixed-signal circuits which rely on variations unique to a specific chip to self-generate a digital “fingerprint.” Most PUFs require a “helper-data” image that is generated during the initial digitization process, also known as Enrollment. Leveraging the chip-unique transformation function of PUFs and encrypted helper data, an unclonable challenge-response mechanism can be impl... » read more

HBM2E Raises The Bar For Memory Bandwidth


AI/ML training capabilities are growing at a rate of 10X per year driving rapid improvements in every aspect of computing hardware and software. HBM2E memory is the ideal solution for the high bandwidth requirements of AI/ML training, but entails additional design considerations given its 2.5D architecture. Designers can realize the full benefits of HBM2E memory with the silicon-proven memory s... » read more

Root Of Trust RT-600 Series Security Anchored in Hardware


Built around a custom 32-bit CPU, the Rambus Root of Trust RT-600 series is at the forefront of a new category of programmable hardware-based security cores. Siloed from the primary processor, it is specifically designed to securely run sensitive code, processes, and algorithms. In addition to the CPU, the RT-600 series contains a large set of hardware blocks arranged around an internal bus fab... » read more

HBM3 Memory: Break Through To Greater Bandwidth


AI/ML’s demands for greater bandwidth are insatiable driving rapid improvements in every aspect of computing hardware and software. HBM memory is the ideal solution for the high bandwidth requirements of AI/ML training, but it entails additional design considerations given its 2.5D architecture. Now we’re on the verge of a new generation of HBM that will raise memory and capacity to new hei... » read more

Servers And The Drive to DDR5


This IDC Technology Spotlight Study, sponsored by Rambus, discusses server demands on DRAM and different workloads. DRAM must dynamically adjust to the needs of these disparate workloads. The history of dynamic random-access memory (DRAM) is characterized by the ability of the technology to adapt to the increasingly specialized real-time memory requirements of the applications that utilize it. ... » read more

Servers And The Drive To DDR5


This IDC Technology Spotlight Study, sponsored by Rambus, discusses server demands on DRAM and different workloads. DRAM must dynamically adjust to the needs of these disparate workloads. The history of dynamic random-access memory (DRAM) is characterized by the ability of the technology to adapt to the increasingly specialized real-time memory requirements of the applications that utilize it. ... » read more

MIPI Drives Performance For Next-Generation Displays


MIPI Alliance technology has helped enable the dramatic growth of the mobile phone market. The function and capabilities of MIPI interface solutions have grown dramatically as well. MIPI DSI-2 has become the leading display interface across a growing range of products including smartphones, AR/VR, IoT appliances, and ADAS/autonomous vehicles. As the application space has expanded, so too have t... » read more

CXL Memory Interconnect Initiative: Enabling A New Era of Data Center Architecture


In response to an exponential growth in data, the industry is on the threshold of a groundbreaking architectural shift that will fundamentally change the performance, efficiency and cost of data centers around the globe. Server architecture, which has remained largely unchanged for decades, is taking a revolutionary step forward to address the growing demand for data and the voracious performan... » read more

Data Center Evolution: Accelerating Computing With PCI Express 5.0


The PCI Express (PCIe) interface is the critical backbone that moves data at high bandwidth between various compute nodes such as CPUs, GPUs, FPGAs, and workload-specific accelerators. The rise of cloud-based computing and hyperscale data centers, along with high-bandwidth applications like artificial intelligence (AI) and machine learning (ML), have pushed PCIe 4 to its limits. In this white p... » read more

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