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Hardware Deployment for Secure AI Using Confidential Computing
By Rambus - 01 Apr, 2026 - Comments: 0

AI’s fast evolution is producing autonomous systems that can operate with minimal human oversight, improve themselves and become effective at decision-making in complex environments. These developments require careful consideration of security and privacy. To limit the overhead performance impact (area, throughput, latency and power), hardware-based security solutions can be deploye... » read more

Multi-Channel Ultra Ethernet TSS Complete Layer
By Rambus - 04 Mar, 2026 - Comments: 0

In the data center environment, the servers, storage and AI/HPC clusters need to move confidential data quickly and securely. Traditionally, RDMA is used as a transport protocol along with the network security based on MACsec and IPsec ESP protocols. To improve efficiency of using Ethernet in AI/HPC systems, the Ultra Ethernet Consortium introduced the new, IP-based transport protocol (UET), al... » read more

PCIe Technology in Switches
By Rambus - 14 Jan, 2026 - Comments: 0

Two benefits of using PCIe switches include accessibility to more endpoints and enabling data center disaggregation. Rambus's Lou Ternullo and Wesley Yung from Astera Labs discuss benefits, use cases, and PCIe technology used in switches in this video from PCI-SIG. Hear more about the technology here. » read more

High Bandwidth Memory (HBM): Everything You Need To Know
By Rambus - 12 Nov, 2025 - Comments: 0

In an era where data-intensive applications, from AI and machine learning to high-performance computing (HPC) and gaming, are pushing the limits of traditional memory architectures, High Bandwidth Memory (HBM) has emerged as a high-performance, power-efficient solution. As industries demand faster, higher throughput processing, understanding HBM’s architecture, benefits, and evolving role in ... » read more

HBM4 Memory: Break Through to Greater Bandwidth
By Rambus - 10 Sep, 2025 - Comments: 0

Delivering unrivaled memory bandwidth in a compact, high-capacity footprint, has made HBM the memory of choice for AI training. HBM4 is the fourth major generation of the HBM standard, with new power management and RAS features. The Rambus HBM4 Controller provides industry-leading performance to 10.0 Gb/s, enabling a memory throughput of over 2.5 TB/s for training systems, generative AI and oth... » read more

MACsec Fundamentals Securing Data in Motion: 2025
By Rambus - 03 Sep, 2025 - Comments: 0

For end-to-end security of data, it must be secured both when at rest (stored on a connected device) and when in motion (communicated between connected devices). For data at rest, a hardware root of trust anchored in silicon provides that foundation upon which all device security is built. Similarly, MACsec (Media Access Control) security anchored in hardware at the foundational communication l... » read more

Scaling DRAM Technology To Meet Future Demands: Challenges And Opportunities
By Rambus - 13 Aug, 2025 - Comments: 0

Since the invention of the 1T1C bit cell more than 50 years ago, DRAMs have become the main memory of choice for processors in computer systems and many consumer electronics devices. As new use computing paradigms have been created, including 3D graphics, cloud computing, smart phones, and AI processing, specialized processors and DRAM memories have been developed that are optimized for these u... » read more

Expanding Server Memory Capabilities With Multiplexed Rank DIMM (MRDIMM) Technology
By Rambus - 16 Jul, 2025 - Comments: 0

The scaling of computational power within a single, packaged semiconductor component continues to rise following a Moore’s law type curve enabling new and more capable applications including machine learning (ML), generative artificial intelligence (AI), and training and deployment of large language models (LLM). On-demand lifestyle applications like language translation, direction finding, a... » read more

DDR5 Client Chipset
By Rambus - 05 Sep, 2024 - Comments: 0

This episode of Ask the Experts discusses DDR5 for client systems with John Eble, VP of Product Marketing, Memory Interface Chips at Rambus. Topics discussed include: The need for advanced chipsets for DDR5 client DIMMs The role of the DDR5 Client Clock Driver (CKD) and its use cases The AI applications driving the need for greater memory performance in client systems Find more... » read more

Data Center Evolution: The Leap to 64 GT/s Signaling with PCI Express 6.1
By Rambus - 05 Jun, 2024 - Comments: 0

The PCI Express (PCIe) interface is the critical backbone that moves data at high bandwidth and low latency between various compute nodes such as CPUs, GPUs, FPGAs, and workload-specific accelerators. With the rapid rise in bandwidth demands of advanced workloads such as AI/ML training, PCIe 6.1 jumps signaling to 64 GT/s with some of the biggest changes yet in the standard. Find more inform... » read more

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