Dependency on DRAM package delay for advanced fly-by is discussed.
Package signal transit delay is an important parameter for high-speed designs like DDR5. Package delay along with PCB delay dictates the data rates of DDR5 interface running at 4.0 Gbps and beyond. From DDR3 (third generation DDR) onwards, daisy chain routing has been widely used as it can support high data rate operations by providing smaller trace stubs and capacitive loadings. Even so, beyond a certain number of loadings, the fly-by starts to have trouble in keeping up with high data rates. One of the limiting factors for fly-by is package delay. To address various limitations of fly-by topology, advanced fly-by topology routing was introduced. Dependency on DRAM package delay for advanced fly-by is discussed in this paper.
Authors: Vinod Arjun Huddar, Rambus Inc., Bangalore, India; Shinyoung Park, Bufferchip, Rambus Inc., San Jose, USA.
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