Exploring The Latest Innovations In MIPI D-PHY And MIPI C-PHY


Introduction  In the ever-evolving landscape of high-performance camera and display technologies, MIPI D-PHY™ and MIPI C-PHY™ specifications continue to lead the charge, setting benchmarks for low power, low latency, and high bandwidth data transmission. Building on the insights from our previous article, “Demystifying MIPI C-PHY/D–PHY Subsystem” – ... » read more

Package Propagation Delay Dependency Of Advanced Fly-By Routing For Next Generation DDR5


Package signal transit delay is an important parameter for high-speed designs like DDR5. Package delay along with PCB delay dictates the data rates of DDR5 interface running at 4.0 Gbps and beyond. From DDR3 (third generation DDR) onwards, daisy chain routing has been widely used as it can support high data rate operations by providing smaller trace stubs and capacitive loadings. Even so, beyon... » read more

Next-Gen Design Challenges


As more heterogeneous chips and different types of circuitry are designed into one system, that all needs to be simulated, verified and validated before tape-out. Aveek Sarkar, vice president of engineering at Synopsys, talks with Semiconductor Engineering about the intersection of scale complexity and systemic complexity, the rising number of corners, and the reduced margin with which to buffe... » read more