tag: system on chip

Why SoC Designers Need Purpose-Built Semiconductor IP Catalog Tools
By Roberto Piacentini Filho - 25 Jul, 2024 - Comments: 0

Semiconductor intellectual property (IP) management, reuse, and change tracking are essential for efficiently creating chip designs based on proven building blocks, reducing your time-to-market, and maintaining good reputations throughout their lifetimes. Unfortunately, many SoC teams attempt to use existing tools like Git for these essential tasks, even though they are unsuitable and inconv... » read more

Resilient And Secure Programmable SoC Accelerator Offload (KAUST)
By Technical Paper Link - 03 Jul, 2024 - Comments: 0

A technical paper titled “Resilient and Secure Programmable System-on-Chip Accelerator Offload” was published by researchers at King Abdullah University of Science and Technology (KAUST). Abstract: "Computational offload to hardware accelerators is gaining traction due to increasing computational demands and efficiency challenges. Programmable hardware, like FPGAs, offers a promising plat... » read more

Competitive Open-Source EDA Tools
By Technical Paper Link - 19 May, 2024 - Comments: 0

A technical paper titled “Basilisk: Achieving Competitive Performance with Open EDA Tools on an Open-Source Linux-Capable RISC-V SoC” was published by researchers at ETH Zurich and University of Bologna. Abstract: "We introduce Basilisk, an optimized application-specific integrated circuit (ASIC) implementation and design flow building on the end-to-end open-source Iguana system-on-chip (... » read more

Modeling And Analyzing Open-Source SoCs For Low-Power Cyber-Physical Systems
By Technical Paper Link - 08 Feb, 2024 - Comments: 0

A technical paper titled “TOP: Towards Open & Predictable Heterogeneous SoCs” was published by researchers at University of Bologna, ETH Zurich, and University of California San Diego. Abstract: "Ensuring predictability in modern real-time Systems-on-Chip (SoCs) is an increasingly critical concern for many application domains such as automotive, robotics, and industrial automation. An... » read more

SoC Integration And Data Transport Architecture Requirements Surge In 2023
By Frank Schirrmeister - 30 Nov, 2023 - Comments: 0

As the holiday season is in full swing, it's retrospection and prediction time! Let's look at what I thought 2023 would look like, review how it turned out, and take a first stab at 2024 predictions. As a spoiler, my biggest surprise was the intensity with which artificial intelligence and machine learning (AI/ML) accelerated since Generative AI was put on the mainstream adoption map last year,... » read more

A HIL Methodology For The SoC Development Flow
By Technical Paper Link - 14 Nov, 2023 - Comments: 0

A technical paper titled “Virtual-Peripheral-in-the-Loop : A Hardware-in-the-Loop Strategy to Bridge the VP/RTL Design-Gap” was published by researchers at University of Bremen and German Research Center for Artificial Intelligence (DFKI). Abstract: "Virtual Prototypes act as an executable specification model, offering a unified behavior reference model for SW and HW engineers. However, b... » read more

A Formal Verification Method To Detect Timing Side Channels In MCU SoCs
By Technical Paper Link - 11 Oct, 2023 - Comments: 0

A technical paper titled “A New Security Threat in MCUs – SoC-wide timing side channels and how to find them” was published by researchers at University of Kaiserslautern-Landau and Stanford University. Abstract: "Microarchitectural timing side channels have been thoroughly investigated as a security threat in hardware designs featuring shared buffers (e.g., caches) and/or parallelism b... » read more

NoC Obfuscation For Protecting Against Reverse Engineering Attacks (U. Of Florida)
By Technical Paper Link - 20 Jul, 2023 - Comments: 0

A technical paper titled "ObNoCs: Protecting Network-on-Chip Fabrics Against Reverse-Engineering Attacks" was published by researchers at University of Florida. Abstract: "Modern System-on-Chip designs typically use Network-on-Chip (NoC) fabrics to implement coordination among integrated hardware blocks. An important class of security vulnerabilities involves a rogue foundry reverse-engineeri... » read more

Fault Awareness And Reliability Improvements In a Fault-Tolerant RISC-V SoC (HARV-SoC)
By Technical Paper Link - 24 Jun, 2023 - Comments: 0

A technical paper titled “Enhancing Fault Awareness and Reliability of a Fault-Tolerant RISC-V System-on-Chip” was published by researchers at University of Montpellier and University of Vale do Itajaí. Abstract: "Recent research has shown interest in adopting the RISC-V processors for high-reliability electronics, such as aerospace applications. The openness of this architecture enables... » read more

Physically Aware NoCs
By Ed Sperling - 06 Mar, 2023 - Comments: 0

More functions, greater security risks, and increasingly complicated integration of IP and various components below 7nm is increasing the time and effort it takes to get a functioning chip out the door. In many of these devices, the network on chip is the glue between various components, but it can take up to 10% to 12% of the total area of the SoC. Andy Nightingale, vice president of product m... » read more

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