Physically Aware NoCs

How to build a better network on chip


More functions, greater security risks, and increasingly complicated integration of IP and various components below 7nm is increasing the time and effort it takes to get a functioning chip out the door. In many of these devices, the network on chip is the glue between various components, but it can take up to 10% to 12% of the total area of the SoC. Andy Nightingale, vice president of product marketing at Arteris IP, talks about how to shrink the NoC area, improve security, and reduce time to market.

Leave a Reply

(Note: This name will be displayed publicly)