Reducing SoC Power With NoCs And Caches


Today’s system-on-chip (SoC) designs face significant challenges with respect to managing and minimizing power consumption while maintaining high performance and scalability. Network-on-chip (NoC) interconnects coupled with innovative cache memories can address these competing requirements. Traditional NoCs SoCs consist of IP blocks that need to be connected. Early SoCs used bus-based archi... » read more

Chiplets Make Progress Using Interconnects As Glue


Breaking up SoCs into their component parts and putting those and other pieces together in some type of heterogeneous assembly is beginning to take shape, fueled by advances in interconnects, complex partitioning, and industry learnings about what works and what doesn't. While the vision of plug-and-play remains intact, getting there is a lot more complicated than initially imagined. It can ... » read more

Accelerate AI SoC Designs with NoC Tiling


Network-on-chip (NoC) tiling technology is revolutionizing AI and machine learning-enabled semiconductor designs. This emerging approach uses proven, robust network-on-chipIP to facilitate scaling, condense design time, speed testing and reduce design risk. It allowsSoC architects to create modular, scalable designs by replicating soft tiles across the chip. Each soft tile represents a self-con... » read more

Data Routing In Heterogeneous Chip Designs


Ensuring data gets to where it's supposed to go at exactly the right time is a growing challenge for design engineers and architects developing heterogeneous systems. There is more data moving around these chips with dozens of targets, which makes routing signals much more complicated. Ronen Perets, senior product marketing manager at Cadence Design Systems, talks about some of the new problems... » read more

Managing Performance in Modern SoC Designs


As industries like automotive, consumer electronics, telecommunications and artificial intelligence (AI) push for greater processing power, efficiency and scalability, system-on-chip (SoC) designs have rapidly evolved to meet these demands. With the growing complexity of modern SoCs, designers face the challenge of managing an increasing number of interconnected IP blocks while ensuring seamles... » read more

Streamlining Complex Semiconductor Designs With IP-XACT-Based Structured Assembly


Semiconductor design is rapidly evolving because technologies such as AI and machine learning (ML) applications push the boundaries of complexity and specialization. Modern chips require hundreds or thousands of IP blocks, leading to significant design challenges. Multi-die architectures, which distribute functional blocks across multiple dice, demand expert planning to ensure connectivity and ... » read more

Optimizing Interconnect Topologies For Automotive ADAS Applications


Designing automotive Advanced Driver Assistance Systems (ADAS) applications can be incredibly complex. State-of-the-art ADAS and autonomous driving systems use ‘sensor fusion’ to combine inputs from multiple sources, typically cameras and optionally radar and lidar units to go beyond passive and active safety to automate driving. Vision processing systems combine specialized AI accelerators... » read more

Cadence Janus NoC System IP


The Cadence Janus Network on Chip (NoC) is a new highly configurable soft IP designed to speed up the system-on-chip (SoC) and full system design cycle by reducing some of the problems associated with large SoCs. With many more processing nodes, as well as memory and I/O nodes designed into the SoC, the interconnect becomes a major design hurdle. Wiring congestion and wire loads introduce ch... » read more

Streamlining SoC Design With Advanced IP And Integration Solutions


As system-on-chip (SoC) complexity grows, so does the necessity for products that seamlessly connect IP and streamline integration processes, minimize manual errors, and enhance productivity. The emphasis on physical awareness across solutions significantly reduces the iterative cycles of NoC placement and routing. By ensuring low latency and high efficiency, these advanced integration solution... » read more

Use of NoC IP Facilitates Tailoring SoC Platform Design into Bespoke SoC Devices


Customer Overview Dream Chip Technologies is a German company that originated from a research think tank initiative comprised of private companies and government-funded organizations in the beginning of 1990. The results from this effort were foundational in establishing German mastery of microelectronics. Dream Chip Technologies started as a design services provider, developing intellectua... » read more

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