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Using SystemC TLM Modeling To Solve AI Data Movement Challenges


In AI silicon, the performance numbers tell only part of the story. Marketing claims often highlight headline metrics such as trillions of operations per second, tensor throughput, matrix dimensions, and accelerator density. But engineers building these systems understand the harder truth. Compute performance matters only when data arrives at the right rate, with the right latency, and without ... » read more

Facilitating Complex SoC Design Through Automation And Integration


The design demands of today’s highly advanced system-on-chip (SoC) devices have long outgrown the capabilities of manual workflows to manage them effectively. As these chips become more complex, only sophisticated, high-performance, and scalable automation can ensure that every component of the SoC functions seamlessly. The SoC integration challenge A fundamental aspect of SoC design is the... » read more

Efficiency Defines The Future Of Data Movement


For decades, chip performance was measured by how much raw compute could be packed onto a die. However, that equation has changed. Moving data across a system-on-chip (SoC) now consumes more energy than the computations it performs. Efficient data movement has become a significant challenge for next-generation SoC designs. AI workloads are multiplying, hyperscale data centers are approaching po... » read more

The Future Of SoC Design Is Data Movement


The semiconductor industry is experiencing rapid advances in chiplet adoption, high-bandwidth memory, Compute Express Link (CXL) fabrics, and automotive zonal architectures. As we move into the second half of 2025, the only sustainable path forward is a layered, physically aware, and automated interconnect methodology that can keep pace with escalating complexity. This article is Part Two of... » read more

A Smarter Path To Chiplets Through An Enhanced Multi-Die Solution


The rise of artificial intelligence (AI) is advancing at breakneck speed, pushing computing demands. At the same time, Moore’s Law slows, making monolithic devices increasingly cost-prohibitive and harder to scale. As traditional monolithic scaling hits the wall, the solution is to disaggregate the design into multiple dies, known as chiplets. These chiplets are mounted on a common substrate ... » read more

Data Movement Is the Energy Bottleneck of Today’s SoCs


In today’s AI-focused semiconductor landscape, raw compute performance alone no longer defines the effectiveness of a system-on-chip (SoC). The efficiency of data movement across the chip has become just as important. Whether designed for data centers or edge AI devices, SoCs must now prioritize data transport as a core architectural consideration. Moving data efficiently across the silicon f... » read more

Achieving Lower Power, Better Performance, And Optimized Wire Length In Advanced SoC Designs


In system-on-chip (SoC) design, wire length refers to the total physical distance of interconnects within a network-on-chip (NoC). It is a critical parameter that influences performance, power consumption, and manufacturing costs. Today’s SoCs incorporate numerous IP blocks connected by multiple complex NoCs and require efficient management of wire lengths. Excessive wire length increases lat... » read more

From DIY To Advanced NoC Solutions: The Future Of MCU Design


The evolution of microcontrollers (MCUs) has significantly transformed embedded systems, shifting from simple, standalone processors to complex, multifunctional units that rival traditional systems-on-chip (SoCs). These advancements are fueled by the demand for increased computational efficiency, cutting-edge features like AI and machine learning (ML) integration, and the need to address growin... » read more

2024 Set The Stage For NoC Interconnect Innovations In SoC Design


What a year it’s been for Arteris! Reflecting on 2024, the company achieved exciting milestones and breakthroughs that pushed the boundaries of system-on-chip (SoC) design. A game-changing new technology was unveiled, a major product was launched, and existing solutions were tailored for AI, automotive, high-performance computing (HPC) and more. Along the way, we welcomed new partners and ... » read more

Scaling AI Chip Design With NoC Soft Tiling


Tiling is about repeating modular units within the same chip to enhance scalability and efficiency; chiplets involve combining different silicon pieces to achieve a more diverse and powerful system within a single package. Network-on-chip (NoC) soft tiling is complimentary but distinct from chiplets described above as it repeats modular units inside a NoC design. Soft tiling within a NoC off... » read more

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