The Future Of SoC Design Is Data Movement

The semiconductor industry is experiencing rapid advances in chiplet adoption, high-bandwidth memory, Compute Express Link (CXL) fabrics, and automotive zonal architectures. As we move into the second half of 2025, the only sustainable path forward is a layered, physically aware, and automated interconnect methodology that can keep pace with escalating complexity.

This article is Part Two of Data Movement Is The Energy Bottleneck Of Today’s SoCs, which states that data movement, not compute, has become the limiting factor for performance and energy efficiency in complex chips. That reality remains true today, with even greater urgency. The blog below provides an update on industry requirements, design consequences, and architectural patterns shaping system-on-chip (SoC) data movement strategies.

Industry requirements and consequences

Emerging technologies are reshaping SoC design, each bringing new requirements and risks. These shifts, from chiplet packaging to off-chip fabrics and automotive safety mandates, place new stress on the interconnect. The result is a greater risk of delays, inefficient bandwidth use, and certification setbacks.

• Chiplets and Multi-Die Scaling: Scaling beyond a single die has become essential for artificial intelligence (AI) and high-performance computing (HPC). Instead of building one monolithic chip, designers now split systems into multiple dies, often fabricated on different process nodes to optimize yield and cost. The challenge is to ensure that software and workloads continue to experience the system as a single, unified compute environment. Non-Uniform Memory Access (NUMA) is an architecture where access times to memory vary depending on the location of the data relative to the processor(s). Without NUMA-aware coherency, performance varies unpredictably, latency grows erratic, and bandwidth is wasted. This is why the Universal Chiplet Interconnect Express (UCIe) standard is becoming so important. It provides a foundation for die-to-die connectivity, essentially a “PCIe for chiplets.” UCIe reduces fragmentation and ensures that chiplets from different vendors interoperate predictably within the same package. Note, however, that implementation maturity across tools and vendors is still evolving.
• HBM/DDR Bandwidth: High-bandwidth memory (HBM4) and next-generation DDR provide unprecedented throughput, but raw bandwidth is only part of the equation. Tail latency and head-of-line blocking can waste a significant portion of that capacity if traffic management is not handled correctly. Think of HBM as a multi-lane highway. Without traffic rules, a minor fender bender can bring the entire freeway to a standstill. In SoCs, the equivalent solution is an interconnect with robust quality of service (QoS) features that prioritize latency-sensitive traffic while ensuring that bulk data transfers flow smoothly.
• CXL 3.x Fabrics: Compute Express Link (CXL) 3.x introduces the ability to pool memory and accelerators beyond the SoC boundary. This promises enormous flexibility for data center workloads but creates new requirements inside the SoC. On-chip fabrics must be able to “speak CXL” through proxy logic, ensuring that external devices exchange data coherently with CPUs and caches. Without this alignment, designers risk protocol mismatches, expensive overprovisioning, and inefficient workarounds.
• Automotive Zonal Architectures: The automotive industry is transforming from dozens of distributed electronic control units (ECUs) to a smaller number of centralized zonal controllers. These zonal architectures demand safety-certified interconnects that guarantee isolation between functions. For example, changing the radio station cannot, under any circumstances, interfere with braking. Certification to ISO 26262 at the highest ASIL D level requires partitioning, diagnosability, and interference-free operation. Without this, automotive programs can face delays of a year or more, an unacceptable risk in an industry with long product cycles and high safety stakes.
• Backend Congestion: Traditional buses and crossbars are no longer sustainable. As more IP blocks are added, wire counts grow quadratically, clogging routing resources and creating severe congestion in back-end design flows. This wire bloat forces expensive fixes late in the design cycle. A physically aware network-on-chip (NoC) reduces wire counts early in the flow, easing pressure on routing and preventing schedule slips and missed tape-outs.
• Integration Complexity: Modern SoCs contain millions of configuration and status registers (CSRs) and thousands of connections. Managing these with spreadsheets and manual flows is unsustainable. The result is an inevitable drift between specification, RTL, and firmware. The industry increasingly turns to machine-readable golden specifications, such as IP-XACT or SystemRDL, that automatically generate RTL, firmware headers, and documentation. This keeps all representations synchronized, reduces errors, and accelerates time to market.

Architecture patterns for Q3’2025 and beyond

SoC designers are embracing several key architectural patterns to meet the abovementioned challenges.

• Layered Interconnect: Figure 1 shows that modern NoCs are best understood as layered systems, much like traditional computer networks. Protocols such as AXI, CHI, or ACE are adapted at the transaction layer. The transport layer handles routing and QoS. The physical layer ensures closure with pipelines and serialization. This approach enables predictable scaling while maintaining safety.

Fig. 1: Modern NoCs are best understood as layered systems. (Source: Arteris)

• Coherency Across Dies: Directory-based coherency models are expanding to support heterogeneous processors, such as CPUs, GPUs, and NPUs, spread across multiple dies. Maintaining coherency is critical for predictable performance, particularly with NUMA policies aligned to UCIe and CXL standards. By treating memory as a shared, coherent resource, SoC designers can integrate diverse chiplets while avoiding latency spikes and inefficient data transfers.
• Safety, Security, and Validation: As SoCs take on more critical roles, safety, security, and validation cannot be afterthoughts:
  • Safety: ISO 26262 ASIL D readiness requires error correction (ECC), lockstep support, delay monitors, and formal safety deliverables.
  • Security: On-chip firewalls, isolation domains, and compliance checks protect against errant or malicious masters.
  • Validation: Stress traffic generation, latency tail analysis, and formal deadlock verification ensure that designs meet real-world demands.

Common pitfalls and consequences

Even with advances in chiplet packaging, memory systems, off-chip fabrics, automotive zonal designs, and layered interconnects, design teams continue to encounter recurring pitfalls—Table 1 highlights where teams often stumble and the impact it can have.

Table 1: Common pitfalls and impacts. (Source: Arteris)

Over-reliance on buses and crossbars, manual register management, or a coherency everywhere mindset often undermines the very progress the new technologies enable. These issues underscore the importance of early planning, automation, and awareness of system-level consequences in advanced SoC design.

Evaluation checklist for SoC architects

At Arteris, our applications engineers routinely ask customers a suite of questions. These are the same questions every SoC architect should be asking themselves:

• Does the fabric scale across single- and multi-die?
• Are QoS and latency guarantees proven under load?
• Is pipeline insertion automated and physically aware?
• Can the fabric handle heterogeneous coherency and NUMA policies?
• Are safety and security features certifiable and complete?
• Is integration driven from golden specifications for connectivity and registers?

This checklist is often a wake-up call for teams that want to build their own interconnect. Data movement is not an afterthought; it is the backbone of the system.

Redefining what’s possible

Rather than viewing interconnect simply as a response to today’s scaling pressures, it should be understood as an enabler of entirely new design freedoms. New complex SoC designs will require flows that are automated and physically aware while also being coordinated with standards such as UCIe and CXL. This alignment ensures that diverse chiplets can be integrated predictably, with safety and security preserved as systems scale. The result is not just efficiency but the ability to redefine the next generation of systems.

At Arteris, we have spent years helping customers navigate these challenges. Our FlexGen technology makes interconnect physically aware, directly incorporating floorplan constraints, congestion analysis, and timing goals into the flow so data paths converge with physical design.

FlexNoC and Ncore extend this foundation across non-coherent and coherent implementations, enabling efficient bandwidth use, predictable latency, and synchronized access to shared data across heterogeneous processors. Together with Arteris Magillem products for integration automation and metadata management, these solutions provide the end-to-end infrastructure that moves data reliably in future-ready SoCs, validated across multiple generations of successful silicon.