tag: UCIe

Integrating Ethernet, PCIe, And UCIe For Enhanced Bandwidth And Scalability For AI/HPC Chips
By Madhumita Sanyal - 12 Dec, 2024 - Comments: 0

By Madhumita Sanyal and Aparna Tarde Multi-die architectures are becoming a pivotal solution for boosting performance, scalability, and adaptability in contemporary data centers. By breaking down traditional monolithic designs into smaller, either heterogeneous or homogeneous dies (also known as chiplets), engineers can fine-tune each component for specific functions, resulting in notable im... » read more

Chiplet Interconnects Add Power And Signal Integrity Issues
By Adam Kovac - 12 Dec, 2024 - Comments: 0

The flexibility and scalability offered by chiplets make them an increasingly attractive choice over planar SoCs, but the rollout of increasingly heterogeneous assemblies adds a variety of new challenges around the processing and movement of data. Nearly all of the chiplets in use today were designed in-house by large systems companies and IDMs. Going forward, third-party chiplets will begin... » read more

Critical Design Considerations For High-Bandwidth Chiplet Interconnects (TSMC)
By Technical Paper Link - 26 Nov, 2024 - Comments: 0

A new technical paper titled "High-Bandwidth Chiplet Interconnects for Advanced Packaging Technologies in AI/ML Applications: Challenges and Solutions" was published by researchers at TSMC. Abstract: "The demand for chiplet integration using 2.5D and 3D advanced packaging technologies has surged, driven by the exponential growth in computing performance required by Artificial Intelligence a... » read more

Chip Industry Week In Review
By The SE Staff - 22 Nov, 2024 - Comments: 0

SK hynix started mass production of 1-terabit  321-high NAND, with availability scheduled for the first half of next year. Rapidus will receive an additional ¥200 billion yen ($1.28B) from the Japanese government beginning in fiscal year 2025, reports Nikkei. This is on top of ¥920 billion yen ($5.98B) Rapidus has already received from the government in support of its goal to reach commer... » read more

Analysis Of Multi-Chiplet Package Designs And Requirements For Production Test Simplification
By Vineet Pancholi - 21 Nov, 2024 - Comments: 1

In recent years there has been a sharp rise of multi-die system designs. Numerous publications targeting a large variety of applications exist in the public domain. One presentation [2] on the IEEE’s website does a good job of detailing the anecdotal path of multi-die systems by way of chiplet building blocks integrated within a single package [2]. The presentation includes references to a ha... » read more

Why 40G UCIe IP?
By Aparna Tarde - 31 Oct, 2024 - Comments: 0

AI applications are bringing new challenges to the semiconductor industry. There is an increased demand for greater bandwidth, especially for compute and networking applications to support the high data processing required by deep learning and machine learning algorithms. The requirements for these AI applications are different for die-to-die interfaces. Let’s take 100Tb networking switches a... » read more

Chiplets Make Progress Using Interconnects As Glue
By Ann Mutschler - 31 Oct, 2024 - Comments: 0

Breaking up SoCs into their component parts and putting those and other pieces together in some type of heterogeneous assembly is beginning to take shape, fueled by advances in interconnects, complex partitioning, and industry learnings about what works and what doesn't. While the vision of plug-and-play remains intact, getting there is a lot more complicated than initially imagined. It can ... » read more

Barriers To Chiplet Sockets
By Brian Bailey - 30 Sep, 2024 - Comments: 0

Experts At The Table: Demand for chiplets is growing, but debate continues about whether standards and general-purpose chiplets will kick-start the commercialization boom, or whether success will come through customization of those chiplets. Semiconductor Engineeering sat down to discuss these and other related issues with Elad Alon, CEO of Blue Cheetah; Mark Kuemerle, vice president of technol... » read more

What Comes After HBM For Chiplets
By Brian Bailey - 18 Sep, 2024 - Comments: 0

Experts At The Table: Semiconductor Engineering sat down to discuss what will trigger the creation of a commercial chiplet marketplace, and what those chiplet-based designs will look like, with Elad Alon, CEO of Blue Cheetah; Mark Kuemerle, vice president of technology at Marvell; Kevin Yee, senior director of IP and ecosystem marketing at Samsung; Sailesh Kumar, CEO of Baya Systems; and Tanuja... » read more

Defining The Chiplet Socket
By Brian Bailey - 29 Aug, 2024 - Comments: 0

Experts At The Table: The semiconductor industry has been buzzing with the possibilities surrounding chiplets, but so far this packaging technology has been confined to large semiconductor companies that are vertically integrated. The industry has been attempting to open this up to a broader group of people. To work out what this means for chiplets, and what standardization will be required, Se... » read more

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