tag: UCIe

The Evolution Of UCIe
By Ed Sperling - 02 Jun, 2026 - Comments: 0

Since it was released in March 2022, the Universal Chiplet Interconnect Express (UCIe) has grown from a basic way of connecting two dies together into a comprehensive specification that can ensure the handoff of data between various components in an advanced package, as well as validate the chiplets within that package. Mayank Bhatnagar, director of product marketing at Cadence, talks about the... » read more

Options Grow For Standardizing Data Movement And Sharing Resources
By Ed Sperling - 20 May, 2026 - Comments: 0

Semiconductor Engineering sat down to discuss memory interfaces, interconnects, and memory access scaling with Madhumita Sanyal, senior director of technical product management at Synopsys; Swadesh Choudhary, senior principal engineer at Intel; Siamak Tavallaei, senior principal engineer at Samsung SSI; and Mohsen Asad, senior director of technology at Credo. What follows are excerpts of a disc... » read more

Confusion Grows With More Interconnect Options And Tradeoffs
By Liz Allan - 18 May, 2026 - Comments: 0

Key Takeaways: Designers are frequently evaluating 5 or more different interconnects in a single system, each with a distinct purpose. While chip-to-chip (PCIe) and die-to-die (UCIe, BoW) technologies seem to be solving a similar problem, in practice they bring different challenges. PCIe, CXL, NVLink, and UALink are all active in the hyperscaler space, but Ethernet-based technologies... » read more

Chiplet Standards Aim For Plug-n-Play
By Bryon Moyer - 16 Apr, 2026 - Comments: 0

Key Takeaways Die-to-die chiplet standards are only the beginning. Many more standards are necessary for a chiplet marketplace. A number of such standards have either had initial versions released or are in progress. Existing work covers packaging, a system architecture, various design kits, a universal link layer, and updates to BoW. Today’s chiplets exist in silos. In a ... » read more

Verifying Scale-Up And Scale-Out In Data Centers
By Ed Sperling - 26 Feb, 2026 - Comments: 0

Semiconductor Engineering sat down to discuss challenges and solutions for data center build-out and build-up with Gordon Allan, Siemens EDA director of verification IP; Rishi Chugh, vice president of product marketing for network switching at Marvell; Saravanan Kalinagasamy, senior director of ASIC design and validation at Astera Labs; and Jalaj Gupta, product engineering lead at Siemens EDA. ... » read more

UCIe’s Major Technical Components Are Now In Place
By Bryon Moyer - 12 Feb, 2026 - Comments: 0

Key Takeaways UCIe 3.0 doubles bandwidth and enhances manageability, addressing new use cases and following an annual update cycle since 2023. The growing demand for chiplet-based architectures in AI data centers is driven by the limitations of monolithic chips, making inter-chiplet communication and connectivity crucial. While UCIe was initially seen as feature-heavy, many of its ma... » read more

Chiplet Fundamentals For Engineers: eBook
By Bryon Moyer - 02 Feb, 2026 - Comments: 1

Multi-die assemblies are the next phase of Moore's Law, scaling up and out  to improve performance and add flexibility into designs. By decomposing SoCs into building blocks, yield improves for the individual dies and overall performance increases because a chip is no longer bound by reticle limits. But this is much harder than it sounds. Chiplets don't just snap together like LEGOs, and so... » read more

Automated High-Speed Interface Routing in Multi-Die Designs
By Synopsys - 28 Jan, 2026 - Comments: 0

2.5D and 3D Multi-die design is revolutionizing chip integration by enabling thousands of high-speed connections between dies (also called chiplets). Discover how close placement of dies boosts bandwidth, minimizes latency, and maximizes data throughput. Read this white paper to find out about the importance of interconnectivity planning and die-to-die signal routing for successful m... » read more

3D-IC Market Outlook: Technology Roadmaps, Readiness, And Design Implications
By Reela Samuel - 23 Dec, 2025 - Comments: 0

The 3D-IC market outlook is entering a decisive phase as the semiconductor industry transitions beyond the limits of traditional Moore's Law scaling. As performance, power efficiency, and system complexity outpace what planar integration can deliver economically, vertical integration and heterogeneous system design are no longer experimental; they are becoming foundational. Advanced packagin... » read more

Tracking Your Preferences
By Brian Bailey - 23 Dec, 2025 - Comments: 0

I like to use my last blog of the year to focus on you, the reader. You provide valuable feedback to me and the rest of the team at Semiconductor Engineering. What do you want to see us write about? How in-depth should things be? This is always a balance between the amount of information provided and the rate at which readers tire with an article. My focus is the channels I write for – Sys... » read more

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