Sidestepping Moore’s Law


Calvin Cheung, vice president of engineering at ASE, sat down with Semiconductor Engineering to talk about advanced packaging, the challenges involved with the technology, and the implications for Moore’s Law. What follows are excerpts of that conversation. SE: What are some of the big issues with IC packaging today? Cheung: Moore’s Law is slowing down, but transistor scaling will co... » read more

5 Observations From Intel’s Event


Not long ago, Intel hosted its “Architecture Day,” where top executives from the chip giant revealed the company’s latest products and next-generation technologies. The company also discussed its strategy. To be sure, it’s a critical time for Intel. In June, Brian Krzanich was forced out as chief executive and the company is still looking for a permanent CEO. Plus, Intel has delayed it... » read more

Accurate, fast P2P resistance extraction for unconventional geometries


Accurately measuring interconnect resistance is fundamental to ensuring circuit reliability. Applications that use unconventional metal structures and multiple probe points require enhanced fracturing techniques to extract P2P resistance quickly and accurately. To read more, click here. » read more

The Case For Chiplets


Kandou’s Amin Shokrollahi looks at what’s behind the momentum for a LEGO-like approach, where the challenges are, and how the cost compares with other approaches. https://youtu.be/7QHEeagdLzk     ___________________________________ Find more tech talk videos here .   » read more

Die-To-Die Interconnects For Chip Disaggregation


Today, data growth is at an unprecedented pace. We’re now looking at petabytes of data moving into zettabytes. What that translates to is the need for considerably more compute power and much more bandwidth to process all that data. In networking, high-speed SerDes PHYs represent the linchpin for blazing fast back and forth transmission of data in data centers. In turn, demand is increasin... » read more

The Materials Side Of AI


As we enter the foundry 7nm and below technology nodes, tungsten fill for contacts has reached the physical limits of scaling and copper used in the lowest level interconnects is facing challenges on multiple fronts. Solving these issues will require a new conducting material, namely cobalt. This transition can enable continued device scaling and less power consumption per computation. Follo... » read more

Embedded FPGA Design Considerations


Geoff Tate, CEO of Flex Logix, talks about interconnects, memory, different design approaches, and why foundry processes are critical to eFPGA design. https://youtu.be/FngrgDnJn9c » read more

Dealing With Resistance In Chips


Chipmakers continue to scale the transistor at advanced nodes, but they are struggling to maintain the same pace with the other two critical parts of the device—the contacts and interconnects. That’s beginning to change, however. In fact, at 10nm/7nm, chipmakers are introducing new topologies and materials such as cobalt, which promises to boost the performance and reduce unwanted resist... » read more

Power/Performance Bits: June 19


Tandem solar reaches 25.2% efficiency In the push for ever-more efficient solar panels, researchers are turning to tandem, or double-junction, photovoltaics. Tandem solar panels use two different types of solar cell capable of absorbing different wavelengths of light stacked on top of each other to maximize the conversion of light rays into electrical power. Recently, two groups have reache... » read more

Complexity, Reliability And Cost


Peter Schneider, director of Fraunhofer's Engineering of Adaptive Systems Division, sat down with Semiconductor Engineering to talk about future challenges in complexity, time to market and reliability issues, advanced packaging architectures, and the impact of billions of connected devices. What follows are excerpts of that discussion. SE: What is the biggest challenge you see in the semico... » read more

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