tag: interconnects

Here At Last! Automated Verification Of Heterogeneous 2D/3D Package Connectivity
By Michael Walsh - 25 Jul, 2024 - Comments: 0

By Michael Walsh and Jin Hou with Todd Burkholder The heterogeneous integration of multiple ICs in a single package along with high-performance, high-bandwidth memory is critical for many high-performance computing applications. After everything has been heterogeneously integrated and packaged, such designs feature complex connectivity with many hundreds of thousands of connections, making i... » read more

Optimizing Interconnect Topologies For Automotive ADAS Applications
By Ashley Stevens - 25 Jul, 2024 - Comments: 0

Designing automotive Advanced Driver Assistance Systems (ADAS) applications can be incredibly complex. State-of-the-art ADAS and autonomous driving systems use ‘sensor fusion’ to combine inputs from multiple sources, typically cameras and optionally radar and lidar units to go beyond passive and active safety to automate driving. Vision processing systems combine specialized AI accelerators... » read more

Essential Insights for Design PCIe 6.0 Interconnects
By Keysight - 24 Jul, 2024 - Comments: 0

PCI Express (PCIe) is a serial communication protocol that has progressed through generations to enhance data rates and functionality. The latest version, PCIe 6.0, doubles the data rate to 64 GT/s, enabling up to 256 GB/s of bandwidth in an x16 configuration. The technology incorporates PAM4 signaling and forward error correction to maintain high speeds with improved signal integrity and relia... » read more

Survey of CXL Implementations and Standards (Intel, Microsoft)
By Technical Paper Link - 22 Jul, 2024 - Comments: 0

A new technical paper titled "An Introduction to the Compute Express Link (CXL) Interconnect" was published by researchers at Intel Corporation, Microsoft, and University of Washington. Abstract "The Compute Express Link (CXL) is an open industry-standard interconnect between processors and devices such as accelerators, memory buffers, smart network interfaces, persistent memory, and solid-... » read more

SiC Power Electronics Packaging: Floating Die Structure and Liquid Metal Fluidic Connection (Cambridge U. )
By Technical Paper Link - 17 Jul, 2024 - Comments: 0

A new technical paper titled "Liquid Metal Fluidic Connection and Floating Die Structure for Ultralow Thermomechanical Stress of SiC Power Electronics Packaging" was published by researchers at Cambridge University. Abstract "Coefficients of thermal expansion (CTE) of various materials in packaging structure layers vary largely, causing significant thermomechanical stress in power electroni... » read more

Cadence Janus NoC System IP
By Cadence - 17 Jul, 2024 - Comments: 0

The Cadence Janus Network on Chip (NoC) is a new highly configurable soft IP designed to speed up the system-on-chip (SoC) and full system design cycle by reducing some of the problems associated with large SoCs. With many more processing nodes, as well as memory and I/O nodes designed into the SoC, the interconnect becomes a major design hurdle. Wiring congestion and wire loads introduce ch... » read more

Ruthenium Interconnects On Tap
By Katherine Derbyshire - 20 Jun, 2024 - Comments: 0

Chipmakers' focus on new interconnect technology is ramping up as copper's effectiveness continues to diminish, setting the stage for a significant shift that could improve performance and reduce heat at future nodes and in advanced packages. The introduction of copper interconnects in 1997 upended the then-standard tungsten via/aluminum line metallization scheme. Dual damascene integration ... » read more

Interconnects: Criteria For Alternative Metal Benchmarking And Selection (Imec, KU Leuven)
By Technical Paper Link - 19 Jun, 2024 - Comments: 0

A technical paper titled “Selecting Alternative Metals for Advanced Interconnects” was published by researchers at imec and KU Leuven. Abstract “Today, interconnect resistance and reliability are key limiters for the performance of advanced CMOS circuits. As transistor scaling is slowing, interconnect scaling has become the main driver for circuit miniaturization, and interconnect lim... » read more

Materials And Technologies For High Temperature, Resilient Electronics
By Technical Paper Link - 07 May, 2024 - Comments: 0

A technical paper titled “Materials for High Temperature Digital Electronics” was published by researchers at University of Pennsylvania, Air Force Research Laboratory, and Ozark Integrated Circuits. Abstract: "Silicon microelectronics, consisting of complementary metal oxide semiconductor (CMOS) technology, have changed nearly all aspects of human life from communication to transportatio... » read more

Interconnects Essential To Heterogeneous Integration
By Karen Heyman - 28 Mar, 2024 - Comments: 0

Designing and manufacturing interconnects is becoming more complex, and more critical to device reliability, as the chip industry shifts from monolithic planar dies to collections of chips and chiplets in a package. What was once as simple as laying down a copper trace has evolved into tens of thousands of microbumps, hybrid bonds, through-silicon vias (TSVs), and even junctions for optical ... » read more

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