tag: interconnects

Untangling Chip Traffic Jams
By Liz Allan - 23 Jul, 2026 - Comments: 0

Key Takeaways: Defining all possible cases of coherent and non-coherent traffic is non-trivial, and designers need to use a mix of hardware-assisted verification and simulation tools to do so. For NoCs connecting multiple dies, simulation is challenging due to the very large number of interconnects and multiphysics issues involving thermal and crosstalk. Advanced verification approac... » read more

Graph Transformer Speeds IC Interconnect Signal Integrity Analysis (Buffalo, Stuttgart, IBM)
By Technical Paper Link - 20 Jul, 2026 - Comments: 0

Researchers at the University at Buffalo, University of Stuttgart, and IBM Research published "SI-GT: Fast Interconnect Signal Integrity Analysis For Integrated Circuit Design Via Graph Transformers." Abstract Excerpt: “In this paper, we propose Si-GT, a novel transformer-based model for fast and accurate signal integrity analysis in IC interconnects.” Find the technical paper here. April... » read more

NbAs Nanowires Show Lower Resistivity as Interconnect Dimensions Shrink (Cornell, NYCU, IBM et al.)
By Technical Paper Link - 20 Jul, 2026 - Comments: 0

Researchers at Cornell University, National Yang Ming Chiao Tung University, IBM Research, Johns Hopkins University, et al. published a technical paper titled “Surface-dominant transport in Weyl semimetal NbAs nanowires for next-generation interconnects.” Abstract Excerpt: “ We report the synthesis of Weyl semimetal niobium arsenide (NbAs) nanowires through thermomechanical nanomolding... » read more

Arm Neoverse CMN-700: Performance Analysis Methodology
By Arm - 08 Jul, 2026 - Comments: 0

System performance on modern System-on-Chip (SoC) platforms is increasingly determined by behavior beyond the processing elements. While processor microarchitectures continue to deliver high instruction throughput, overall application performance is often constrained by shared system resources such as caches, memory controllers, and the coherent interconnect that connects them. On Arm Neover... » read more

I/O Design Challenges Grow In AI Data Centers And HPC Clusters
By Liz Allan - 25 Jun, 2026 - Comments: 0

Key Takeaways: A designer’s choice of I/O connectors and interconnect protocols can be the difference between a massively profitable AI chip and a flop. I/O tradeoffs impact airflow, cooling, rack design, power coming into the rack, and other critical aspects of HPC chip design. Reliability is paramount, so standards must be followed, and I/Os need redundant pins. Other innovations... » read more

How To Build Billions of Bumps
By Bryon Moyer - 18 Jun, 2026 - Comments: 0

Key Takeaways: Hybrid bonding can result in a package containing billions (and eventually trillions) of connections. Building that many connections successfully requires extreme process uniformity across a wafer. Inspection isn’t practical, and test benefits from internal test mechanisms. Hybrid bonding allows unprecedented signal pitch, but fully populating dies and inter... » read more

Swapping Out Chiplets: I/Os Vs. Compute
By Liz Allan - 28 May, 2026 - Comments: 0

Key Takeaways: Companies can save time and money by swapping out a compute, memory, or I/O chiplet to gain technology improvements, while keeping the other dies stable. Chip architects may choose to keep their I/Os stable and swap out compute to move from a 5nm process node to 3nm to achieve performance and power improvements, or swap out memory from LPDDR5X to LPDDR6. Swapping out... » read more

Using SystemC TLM Modeling To Solve AI Data Movement Challenges
By Andy Nightingale - 28 May, 2026 - Comments: 0

In AI silicon, the performance numbers tell only part of the story. Marketing claims often highlight headline metrics such as trillions of operations per second, tensor throughput, matrix dimensions, and accelerator density. But engineers building these systems understand the harder truth. Compute performance matters only when data arrives at the right rate, with the right latency, and without ... » read more

Large-scale, SRAM-based LLM Inference Deployment (Groq)
By Technical Paper Link - 21 May, 2026 - Comments: 0

A new technical paper, "SHIP: SRAM-Based Huge Inference Pipelines for Fast LLM Serving," was published by researchers at Nvidia, with work done while at Groq. Abstract "The proliferation of large language models (LLMs) demands inference systems with both low latency and high efficiency at scale. GPU-based serving relies on HBM for model weights and KV caches, creating a memory bandwidth b... » read more

Confusion Grows With More Interconnect Options And Tradeoffs
By Liz Allan - 18 May, 2026 - Comments: 0

Key Takeaways: Designers are frequently evaluating 5 or more different interconnects in a single system, each with a distinct purpose. While chip-to-chip (PCIe) and die-to-die (UCIe, BoW) technologies seem to be solving a similar problem, in practice they bring different challenges. PCIe, CXL, NVLink, and UALink are all active in the hyperscaler space, but Ethernet-based technologies... » read more

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