The Materials Side Of AI


As we enter the foundry 7nm and below technology nodes, tungsten fill for contacts has reached the physical limits of scaling and copper used in the lowest level interconnects is facing challenges on multiple fronts. Solving these issues will require a new conducting material, namely cobalt. This transition can enable continued device scaling and less power consumption per computation. Follo... » read more

Embedded FPGA Design Considerations


Geoff Tate, CEO of Flex Logix, talks about interconnects, memory, different design approaches, and why foundry processes are critical to eFPGA design. https://youtu.be/FngrgDnJn9c » read more

Dealing With Resistance In Chips


Chipmakers continue to scale the transistor at advanced nodes, but they are struggling to maintain the same pace with the other two critical parts of the device—the contacts and interconnects. That’s beginning to change, however. In fact, at 10nm/7nm, chipmakers are introducing new topologies and materials such as cobalt, which promises to boost the performance and reduce unwanted resist... » read more

Power/Performance Bits: June 19


Tandem solar reaches 25.2% efficiency In the push for ever-more efficient solar panels, researchers are turning to tandem, or double-junction, photovoltaics. Tandem solar panels use two different types of solar cell capable of absorbing different wavelengths of light stacked on top of each other to maximize the conversion of light rays into electrical power. Recently, two groups have reache... » read more

Complexity, Reliability And Cost


Peter Schneider, director of Fraunhofer's Engineering of Adaptive Systems Division, sat down with Semiconductor Engineering to talk about future challenges in complexity, time to market and reliability issues, advanced packaging architectures, and the impact of billions of connected devices. What follows are excerpts of that discussion. SE: What is the biggest challenge you see in the semico... » read more

Power/Performance Bits: May 22


Sensing without battery power Engineers at the National University of Singapore developed an IoT-focused sensor chip that can continue operating when its battery runs out of energy. The chip, BATLESS, uses a power management technique that allows it to self-start and continue to function under dim light without any battery assistance. The chip can operate in two different modes: minimum-ene... » read more

Tech Talk: eFPGA Timing


Flex Logix's Chen Wang talks about timing for an embedded FPGA and how that differs from ASIC timing. https://youtu.be/n88D1N4IEbs » read more

New Patterning Options Emerging


Several fab tool vendors are rolling out the next wave of self-aligned patterning technologies amid the shift toward new devices at 10/7nm and beyond. Applied Materials, Lam Research and TEL are developing self-aligned technologies based on a variety of new approaches. The latest approach involves self-aligned patterning techniques with multi-color material schemes, which are designed for us... » read more

Why Inductance Is Good for Area, Power and Performance


By Magdy Abadir and Yehea Ismail For chips designed at advanced technology nodes, interconnect is the dominant contributor towards delay, power consumption, and reliability. Major interconnects such as clock trees, power distribution networks and wide buses play a significant role in chip failure mechanisms such as jitter, noise coupling, power distribution droops, and electro-migration. ... » read more

Tech Talk: 5/3nm Parasitics


Ralph Iverson, principal R&D engineer at Synopsys, talks about parasitic extraction at 5/3nm and what to expect with new materials and gate structures such as gate-all-around FETs and vertical nanowire FETs. https://youtu.be/24C6byQBkuI » read more

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