tag: interconnects

Pathfinding Method That Models ECC Overhead for Chiplet Interconnects (UCLA)
By Technical Paper Link - 16 Mar, 2026 - Comments: 0

A new technical paper, "Link Quality Aware Pathfinding for Chiplet Interconnects," was published by researchers at UCLA. Abstract "As chiplet-based integration advances, designers must select among short-reach die-to-die interconnect technologies with widely varying shoreline and areal bandwidth density, energy per bit, reach, and raw bit error rate (BER). Meeting stringent delivered BER ... » read more

Wafer-on-Wafer Hybrid Bonding: Reticle Placements To Achieve Efficient NW Topologies (ETH Zurich)
By Technical Paper Link - 09 Mar, 2026 - Comments: 0

Researchers from ETH Zurich published the new technical paper "Network Design for Wafer-Scale Systems with Wafer-on-Wafer Hybrid Bonding." Abstract "Transformer-based large language models are increasingly constrained by data movement as communication bandwidth drops sharply beyond the chip boundary. Wafer-scale integration using wafer-on-wafer hybrid bonding alleviates this limitation by p... » read more

AI Energy Gap And Chiplets: Why Data Movement Matters
By Ashley Stevens - 26 Feb, 2026 - Comments: 0

At the recent Chiplet Summit 2026 preconference tutorial, the panel session, “Best Way to Make Chiplets Work,” brought together leaders from across the semiconductor ecosystem to tackle one of the most pressing challenges in advanced system design: how do we make heterogeneous, multi-die systems operate as a cohesive, energy-efficient whole for AI? While much discussion focused on st... » read more

An Explosion In Interconnect Complexity
By Bryon Moyer - 22 Jan, 2026 - Comments: 0

For decades, electronics offered two levels of routing structure to manage signals that originate or terminate in an integrated circuit. Recently, that number has risen to five, and while it adds far more flexibility for structuring electronic equipment, it also brings greater complexity and ratchets up the number of design decisions needed to complete a project. This transition has been evo... » read more

Research Bits: Jan. 20
By Jesse Allen - 20 Jan, 2026 - Comments: 0

ALD for Ru wiring Researchers from Ulsan National Institute of Science and Technology (UNIST), Hongik University, and Tanaka Precious Metal Technologies developed an atomic layer deposition (ALD) process for creating chip interconnects using a ruthenium (Ru) precursor with a thermal stability up to 400 °C. The high-temperature ALD process can produce dense, high-quality Ru films without deg... » read more

Shaping The Future Of AI Processors: A Tech Threads Conversation With Jim Keller
By Nandan Nayampally - 25 Nov, 2025 - Comments: 0

I had the pleasure of hosting renowned computer architect and Tenstorrent CEO Jim Keller, on the latest episode of Baya Systems’ Tech Threads podcast. If you haven’t already, listen to get his insights on the need for “open” intelligence architectures and what would be needed to drive the semiconductor industry forward. What is an “open” intelligent architecture and ecosystem? As... » read more

What Is 3D-IC Technology? Fundamentals, Architecture, And Design Concepts
By Reela Samuel - 25 Nov, 2025 - Comments: 0

As process nodes continue to advance into the sub-micron era, the limitations of traditional scaling are becoming increasingly evident. Larger monolithic chips are facing challenges such as higher power density, routing congestion, and reduced yield. Three-dimensional integrated circuits (3D-IC) technology represents a breakthrough approach by stacking multiple dies vertically. This design red... » read more

From Bottleneck to Breakthrough: Scalable Fabric IP for High- Bandwidth AI and HPC Systems
By Baya Systems - 24 Nov, 2025 - Comments: 0

As compute density and heterogeneity grow rapidly in modern SoCs targeting high-performance computing (HPC) and artificial intelligence (AI) workloads, efficient data movement has emerged as a critical performance and power bottleneck. With increasing core counts, high-speed accelerators, and complex memory hierarchies, traditional bus and crossbar-based interconnects fail to scale, resulting i... » read more

New Interconnect Materials Beyond Copper (Florida State Univ., Cornell)
By Technical Paper Link - 14 Nov, 2025 - Comments: 0

A new technical paper titled "Shrinking interconnects beyond copper" was published by researchers at Florida State University and Cornell University. Excerpt "The continuous downscaling of transistors in integrated circuits following Moore’s law—doubling the number of transistors on a microchip about every 2 years—has been an extraordinary feat of engineering, pushing the limits of fu... » read more

HBM Leads The Way To Defect-Free Bumps
By Laura Peters - 11 Nov, 2025 - Comments: 0

High-bandwidth memory stands at the forefront of multiple technology developments as a critical enabler of AI, but it is one of the most difficult modules to manufacture. Leading HBM device makers and foundries must simultaneously handle multi-layer chip stacking, die warpage, and shorter product lifecycles that are shrinking from two years down to just one. But perhaps the most formidable c... » read more

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