Assawer Soussou

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Assawer Soussou is a senior semiconductor process and integration engineer at Lam Research. She received her Ph.D. in Microelectronics & Electronics from the Institut Polytechnique de Grenoble, in Grenoble, France.

Author's Latest Posts

Overcoming BEOL Patterning Challenges At The 3nm Node

By Assawer Soussou - 20 Nov, 2025 - Comments: 0

As complementary metal-oxide semiconductor (CMOS) area shrinks 50% from one node to the next, interconnect critical dimensions (CD) and pitch (or spacing) are under tight demands. At the N3 node, where metal pitch dimensions must be at or below 18 nm,1,2 one of the main interconnect challenges is securing sufficient process margins for CD and edge placement error (EPE). Achieving the... » read more

Optimizing New Interconnect Technologies To Support Next-Generation Semiconductor Devices

By Assawer Soussou - 18 Dec, 2024 - Comments: 0

Interconnects are the wiring system that connect together the components of a semiconductor device and permit these components to work together. One of the key metrics of any semiconductor interconnect scheme is the metal pitch size. Metal pitch is the minimum distance between the centers of two horizontal interconnects in a semiconductor. It's a key metric used to measure the progress of chip ... » read more

BEOL Integration For The 1.5nm Node And Beyond

By Assawer Soussou - 25 Apr, 2022 - Comments: 0

As we approach the 1.5nm node and beyond, new BEOL device integration challenges will be presented. These challenges include the need for smaller metal pitches, along with support for new process flows. Process modifications to improve RC performance, reduce edge placement error, and enable challenging manufacturing processes will all be required. To address these challenges, we investigated th... » read more

The Future Of FinFETs At 5nm And Beyond

By Assawer Soussou - 05 Mar, 2021 - Comments: 0

While contact gate pitch (GP) and fin pitch (FP) scaling continues to provide higher performance and lower power to finFET platforms, controlling RC parasitics and achieving higher transistor performance at technology nodes of 5nm and beyond becomes challenging. In collaboration with Imec, we recently used SEMulator3D virtual fabrication to explore an end-to-end solution to better underst... » read more