The Future Of FinFETs At 5nm And Beyond

Using combined process and circuit modeling to estimate the performance of the next generation of semiconductors.


While contact gate pitch (GP) and fin pitch (FP) scaling continues to provide higher performance and lower power to finFET platforms, controlling RC parasitics and achieving higher transistor performance at technology nodes of 5nm and beyond becomes challenging.

In collaboration with Imec, we recently used SEMulator3D virtual fabrication to explore an end-to-end solution to better understand process variation effects using circuit simulation. For the first time, we developed a methodology of coupling SEMulator3D with BSIM compact modeling to evaluate process variation impacts on circuit performance [1].

The goal of this study was to optimize contact and spacer thickness of an advanced-node finFET design, to improve speed and power performance. To do so, we compared finFET inverter structures that had three different epitaxial (epi) growth shapes and spacer recess levels (figure 1). We investigated the effect of varying the low-k spacer thickness and identified the best performing combination of finFET spacer thickness and S/D epi shape.

Fig. 1: Key process steps comparison of the three structures.

Figure 2 illustrates the methodology of this study. We used three types of software in our modeling: SEMulator3D, BSIM compact modeling, and Spectre circuit simulation. We started by importing a GDS input file into SEMulator3D, so that we could perform process simulation and RC netlist extraction. Various data, including geometry and parasitic data, was then extracted from SEMulator3D to create an annotated RC netlist. This netlist was subsequently coupled with a BSIM compact front-end-of-line (FEOL) device model and provided as input to a Spectre circuit simulation model. This Spectre model was then used to simulate speed and power performance for the three different inverter configurations being evaluated.

Fig. 2: Flow diagram illustrating the methodology of this study.

In figure 3, plots of power as a function of frequency for the three structures (at various VDD and spacer thicknesses) are shown. For each VDD, we noticed a similar power-speed trend for all epi shape geometries: increasing spacer thickness induced a decrease in power. For each epi geometry, there was an optimum spacer thickness that produced maximum speed and optimum (Reff×Ceff). For all spacer thicknesses, a specific epitaxial shape also offered the highest overall performance. We also investigated S/D access resistances (S/D-R) and Gate-to-S/D (GT-S/D) capacitances for the three structures at the optimum spacer thickness, for both NMOS and PMOS structures, in order to better understand the results reported in figure 3.

Fig. 3: Power-Speed plot comparison for three inverters at a VDD varying from 0.5V to 1V (a) and enlarged VDD=0.7V result (b).

This modeling methodology provided valuable insight into the effect of finFET process changes on sub 5 nm device and circuit performance. We coupled SEMulator3D with BSIM compact modeling and Spectre circuit simulation via RC netlist extraction. The effect of process flow changes across three different inverter geometries (using different spacer thicknesses) was successfully evaluated and compared, to achieve the optimal transistor performance. The impact of VDD and low-k spacer variation on speed and power performance was also explored.

[1] Soussou, T. Schram, K. Miyaguchi, I. Chakarov, B. Parvais and J. Ervin, “Evaluation of the impact of source/drain epi implementation on logic performance using combined process and circuit simulation”, SSDM 2020 conference.

Leave a Reply

(Note: This name will be displayed publicly)