tag: process modeling

Exploring Process Scenarios To Improve DRAM Device Performance
By Yu De Chen - 18 Apr, 2024 - Comments: 0

In the world of advanced semiconductor fabrication, creating precise device profiles (edge shapes) is an important step in achieving targeted on-chip electrical performance. For example, saddle fin profiles in a DRAM memory device must be precisely fabricated during process development in order to avoid memory performance issues. Saddle fins were introduced in DRAM devices to increase channel l... » read more

Techniques To Identify And Correct Asymmetric Wafer Map Defects Caused By Design And Process Errors
By James Kim - 22 Feb, 2024 - Comments: 0

Asymmetries in wafer map defects are usually treated as random production hardware defects. For example, asymmetric wafer defects can be caused by particles inadvertently deposited on a wafer during any number of process steps. In this article, I want to share a different mechanism that can cause wafer defects. Namely, that these defects can be structural defects that are caused by a biased dep... » read more

Developing ReRAM As Next Generation On-Chip Memory For Machine Learning, Image Processing And Other Advanced CPU Applications
By Brett Lowe - 18 Jan, 2024 - Comments: 0

In modern CPU device operation, 80% to 90% of energy consumption and timing delays are caused by the movement of data between the CPU and off-chip memory. To alleviate this performance concern, designers are adding additional on-chip memory to their CPUs. Traditionally, SRAM has been the most widely used on-chip CPU memory type. Unfortunately, SRAM is currently limited to a size of hundreds of ... » read more

Improving Semiconductor Yield Using Large Area Analysis
By Jacky Huang - 19 Dec, 2023 - Comments: 0

Design rule checking (DRC) is a technique used during chip design to ensure that a device can successfully be manufactured at high yield. Design rules are established based on the limits and variability of equipment and process technologies in use. DRC checking ensures that a design meets manufacturing requirements and will not result in a chip failure or DRC “violation.” Common DRC rules i... » read more

Analysis Of BEOL Metal Schemes By Process Modeling
By Daebin Yim - 16 Nov, 2023 - Comments: 0

The semiconductor industry has been diligently searching for alternative metal line materials to replace the conventional copper dual damascene scheme, because as interconnect dimensions shrink, the barrier accounts for an increasing fraction of the total line volume. The barrier layer's dimensions cannot be scaled down as quickly as the metal line width (figure 1). Popular barrier materials su... » read more

The Impact Of Channel Hole Profiles On Advanced 3D NAND Structures
By Qingpeng Wang - 19 Oct, 2023 - Comments: 0

In a two-tier 3D NAND structure, the upper and lower channel hole profile can be different, and this combination of different profiles leads to different top-down visible areas. The visible area is the key metric to determine whether the bottom SONO layer can be punched through and ensure that the bit cells connect to the common source line. Performing channel hole profile splits on a silicon w... » read more

Improving Gate All Around Transistor Performance Using Virtual Process Window Exploration
By Sumant Sarkar - 25 Jul, 2023 - Comments: 0

As transistor sizes shrink, short channel effects make it more difficult for transistor gates to turn a transistor ON and OFF [1]. One method to overcome this problem is to move away from planar transistor architectures toward 3D devices. Gate-all-around (GAA) architectures are an example of this type of 3D device [2]. In a GAA transistor, the gate oxide surrounds the channel in all directions.... » read more

Improving DRAM Device Performance Through Saddle Fin Process Optimization
By Taeyon (TY) Oh - 15 Jun, 2023 - Comments: 0

As DRAM technology nodes have scaled down, access transistor issues have been highlighted due to weak gate controllability. Saddle Fins with Buried Channel Array Transistors (BCAT) have subsequently been introduced to increase channel length, prevent short channel effects, and increase data retention times [1]. However, at technology nodes beyond 20nm, securing sufficient device performance (su... » read more

The Impact Of Metal Gate Recess Profile On Transistor Resistance And Capacitance
By Pradeep Nanja - 18 May, 2023 - Comments: 0

In logic devices such as finFETs (field-effect transistors), metal gate parasitic capacitance can negatively impact electrical performance. One way to reduce this parasitic capacitance is to optimize the metal gate recess dimensions. However, there are limits to reducing this capacitance if you simply remove more of the metal material, since this can modify capacitance unexpectedly through chan... » read more

A Comparative Evaluation Of DRAM Bit-Line Spacer Integration Schemes
By Dempsey Deng - 16 Mar, 2023 - Comments: 0

With decreasing dynamic random-access memory (DRAM) cell sizes, DRAM process development has become increasingly difficult. Bit-line (BL) sensing margins and refresh times have become problematic as cell sizes have decreased, due to an increase in BL parasitic capacitance (Cb). The main factor impacting Cb is the parasitic capacitance between the BL and the node contact (CBL-NC) [1]. To reduce ... » read more

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