中文 English

Author's Latest Posts


Using A Virtual DOE To Predict Process Windows And Device Performance Of Advanced FinFET Technology


By Qingpeng Wang, Yu De Chen, Cheng Li, Rui Bao, Jacky Huang, and Joseph Ervin Introduction With continuing finFET device process scaling, micro loading control becomes increasingly important due to its significant impact on yield and device performance [1-2]. Micro-loading occurs when the local etch rate on a wafer is dependent upon existing feature sizes and local pattern density. Uninten... » read more

Micro Loading And Its Impact On Device Performance


In a DRAM structure, the charging and discharging process of capacitor-based memory cells is directly controlled by the transistor [1]. With transistor sizes approaching the lower limits of physical achievability, manufacturing variability and micro loading effects are becoming increasingly critical DRAM performance (and yield) limiters. The transistor’s AA (active area) dimension and profile... » read more

Identifying And Preventing Process Failures At 7nm


Device yield is highly dependent upon proper process targeting and variation control of fabrication steps, particularly at advanced nodes with smaller feature sizes. Traditionally, cross-correlation and analysis of thousands of test data points have been required to identify and prevent process failures. This is very costly in terms of both time and money. Fortunately, semiconductor virtual fab... » read more