Qingpeng Wang

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QingPeng Wang is a senior engineer in the SP&I group for Semiverse Solutions at Lam Research.

Author's Latest Posts

Accelerating GAA Logic Yield Optimization With Digital Twins

By Qingpeng Wang - 18 Jun, 2026 - Comments: 0

Digital twins allow engineers to minimize costly wafer experiments by simulating the entire GAA logic process upfront Machine learning applied to virtual data simultaneously reduces multiple critical failure modes, boosting yield from 1.6% to 87.2% This methodology offers a repeatable, cost-efficient path to accelerate advanced node manufacturing as device complexity grows... » read more

Minimizing Voltage Loss And Improving Yield In Advanced GAA Chips

By Qingpeng Wang - 18 Dec, 2025 - Comments: 0

The problem: As metal pitch scaling shrinks to support the next generation of logic devices, the IR (or voltage) drop from conventional frontside connections has become a major challenge [1,2]. As electricity travels through a chip’s metal wiring, some voltage gets lost because wires have resistance. If the voltage drops too much, the chip’s transistors can’t get enough power and ... » read more

Semiconductor Virtual Fabrication And Its Applications

By Qingpeng Wang - 24 Jul, 2025 - Comments: 0

Semiverse Solutions, particularly SEMulator3D, can enhance semiconductor engineering in several ways. SEMulator3D is a software platform for semiconductor process modeling and virtual fabrication.1 Prototyping and visualization: Virtual fabrication aids in understanding and visualizing complex semiconductor structures in three dimensions, facilitating better design and prototyping. Unit... » read more

Metal-Oxide-Metal Capacitor Simulation And Modeling By Virtual Fabrication

By Qingpeng Wang - 24 Oct, 2024 - Comments: 0

Metal-Oxide-Metal (MOM) capacitors are passive radio frequency (RF) capacitive devices that are a common component in semiconductor logic chips [1]. A SPICE model of a MOM capacitor is typically used by designers during the design and performance evaluation of logic chip RF circuitry. Traditionally, it may take at least 3 months from the completion of the design layout, wafer fabrication, final... » read more

Improving Line Edge Roughness Using Virtual Fabrication

By Qingpeng Wang - 23 Jul, 2024 - Comments: 0

Line edge roughness (LER) is a variation in the width of a lithographic pattern along one edge of a structure inside a chip. Line edge roughness can be a critical variation source and defect mechanism in advanced logic and memory devices and can lead to poor device performance or even device failure. [1~3]. Deposition-etch cycling is an effective technique to reduce line edge roughness. In this... » read more

The Impact Of Channel Hole Profiles On Advanced 3D NAND Structures

By Qingpeng Wang - 19 Oct, 2023 - Comments: 0

In a two-tier 3D NAND structure, the upper and lower channel hole profile can be different, and this combination of different profiles leads to different top-down visible areas. The visible area is the key metric to determine whether the bottom SONO layer can be punched through and ensure that the bit cells connect to the common source line. Performing channel hole profile splits on a silicon w... » read more

Insights Into Advanced DRAM Capacitor Patterning: Process Window Evaluation Using Virtual Fabrication

By Qingpeng Wang - 20 Oct, 2022 - Comments: 0

With continuous device scaling, process windows have become narrower and narrower due to smaller feature sizes and greater process step variability [1]. A key task during the R&D stage of semiconductor development is to choose a good integration scheme with a relatively large process window. When wafer test data is limited, evaluating the process window for different integration schemes can... » read more

Accelerating Semiconductor Process Development Using Virtual Design Of Experiments

By Qingpeng Wang - 17 Mar, 2022 - Comments: 1

Design of Experiments (DOE) are a powerful concept in semiconductor engineering research and development. DOEs are sets of experiments used to explore the sensitivity of experimental variables and their effect on final device performance. A well-designed DOE can help an engineer achieve a targeted semiconductor device performance using a limited number of experimental wafer runs. However, in se... » read more

Using A Virtual DOE To Predict Process Windows And Device Performance Of Advanced FinFET Technology

By Qingpeng Wang - 03 Aug, 2021 - Comments: 0

By Qingpeng Wang, Yu De Chen, Cheng Li, Rui Bao, Jacky Huang, and Joseph Ervin Introduction With continuing finFET device process scaling, micro loading control becomes increasingly important due to its significant impact on yield and device performance [1-2]. Micro-loading occurs when the local etch rate on a wafer is dependent upon existing feature sizes and local pattern density. Uninten... » read more

Micro Loading And Its Impact On Device Performance

By Qingpeng Wang - 02 Nov, 2020 - Comments: 0

In a DRAM structure, the charging and discharging process of capacitor-based memory cells is directly controlled by the transistor [1]. With transistor sizes approaching the lower limits of physical achievability, manufacturing variability and micro loading effects are becoming increasingly critical DRAM performance (and yield) limiters. The transistor’s AA (active area) dimension and profile... » read more

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