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Identifying And Preventing Process Failures At 7nm

Using failure bin classification, yield prediction and process window optimization to predict and enhance yield.

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Device yield is highly dependent upon proper process targeting and variation control of fabrication steps, particularly at advanced nodes with smaller feature sizes. Traditionally, cross-correlation and analysis of thousands of test data points have been required to identify and prevent process failures. This is very costly in terms of both time and money. Fortunately, semiconductor virtual fabrication tools (such as SEMulator3D) are now available so that these experiments can be “virtually” completed. Even before process experiments are executed in silicon, virtual fabrication can be used to understand process interactions and process step sensitivity and to maximize yield.

In this article, we discuss a simple example of performing yield enhancement by virtual fabrication, using failure bin classification, yield prediction and process window optimization at the 7nm technology node.

Yield Enhancement and Bin Classification

A. Failure Bin Definition
Edge placement error is an important failure mode for BEOL yield loss [2]. Consider a simple circumstance, where M1 is split into metal A (MA) and metal B (MB) (known as LELE or where a metal line is used in the self-aligned double patterning (SADP) process), and the via contact (VC) is designed to connect with MB. Process variations of metal CD (or mandrel CD in an SADP process), or VC CD, or metal to VC overlay, will lead to yield loss due to edge placement errors between vias and metal layers. With different CD and overlay combinations, several failure bins can be defined (see Fig. 1):

  1. High resistance (HR): VC and MB overlap area is small;
  2. VC to MA leakage (VML): VC to MA space is small;
  3. MA to MB leakage (MML): MA to MB space is small;
  4. VC to MB open (VMO): VC is disconnected from MB, and there is no overlap area between them, and
  5. VC to MA short (VMS): VC forms a bridge with MA, and there is a direct VC MA overlap area.


Fig. 1: Bin illustration (a) Pass, (b) HR, (c) VML, (d) MML, (e) VMO, (f) VMS

B. Structure Build and Calibration, Failure Bin Generation and Recognition
To demonstrate the concept of yield enhancement by virtual fabrication, a 7 nm VC and M1 process was constructed. After the virtual structure was generated and calibrated, a series of virtual metrology steps were performed. Fig. 2 shows the corresponding measurement positions on the virtual structure that were used to take measurements and classify failures into their appropriate failure bin structures.


Fig.2: Virtual metrology (structure search) (a), VA-MA minimum overlap area, (b) VA-MB minimum space, (c) MA-MB minimum space, (d) VB-MB maximum overlap area.

Based upon a particular specification and rule, the bin type could be classified automatically using these measurement results.

C. Yield Prediction, Bin Count Ranking
In an actual fabrication process, process parameters such as mandrel/Via CDs and overlays are controlled within certain ranges measured against mean (or nominal) and distribution width values. SEMulator3D provides an automated method to execute a DOE and can generate and collect user defined mean values and range width/sigma values. This data can then be used to calculate the pass rate or yield (the ratio of the pass bin to total number of runs at a specified input condition) based upon the collected data and our yield rule. The user can also classify the failure bin type based upon the generated measurement results table and any bin specification rules.

We established a mean shift range and fixed distribution width of the MCD (Mandrel CD), VCD(Via CD), SPT(spacer thickness) and MVO(the mandrel to VC overlay in the X direction), then executed a DOE with 3000 split virtual runs using Monte Carlo simulation. Fig. 3 (a, b) shows a bin summary bar chart and the yield summary table of the bin percentages at four different input conditions. The chart and table provide us with a quantified failure bin ranking at each particular input setting, useful in understanding the yield impact of specific failure modes.


Fig. 3. Yield status at particular MCD/VCD/MVO setting (a) Bin bar chart, (b) Yield summary

D. Process Window Optimization
During process development, this analysis might lead to a series of additional questions. Is the predicted yield acceptable, can the nominal mean values be adjusted to gain better yield, or could the process distribution width be loosened without further yield loss? Also, if the yield results are still not acceptable, is it possible to tighten the distribution width to obtain a targeted yield and how tight should it be? A process window optimization (PWO) function in SEMulator3D can answer these and other optimization questions. The PWO engine can automatically search for optimized mean shift combinations with fixed distribution width, then provide an optimized process window with maximum yield (pass rate) based upon the collected data.

Table 1 displays a yield and process window summary for nominal, optimized, and optimized + tightened SPT width cases. It shows that the yield can be enhanced from 48.4% to 96.6% by simply optimizing the mean shift. We can further tighten the SPT width specification to obtain a target yield of 99%.


Table 1. Yield summary under different input conditions

Conclusion
This article provides insight into yield enhancement through virtual fabrication, including the use of structure build, profile calibration, virtual metrology, failure bin classification, yield prediction and process window optimization techniques. We used a 7 nm 6T SRAM model, with edge placement error induced VC-M1 yield loss. The results showed that yield was enhanced from 48.4% to 99.0% after process window optimization and specification tightening. Virtual fabrication can be used in a broad range of yield enhancement research to accelerate semiconductor process and technology development.

References
[1] http://www.coventor.com/products/semulator3d
[2] Mulkens, Jan, et al. “Overlay and edge placement control strategies for the 7nm node using EUV and ArF lithography.” Extreme Ultraviolet (EUV) Lithography VI. Vol. 9422. International Society for Optics and Photonics, 2015.



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