tag: Coventor

Improving Line Edge Roughness Using Virtual Fabrication
By Qingpeng Wang - 23 Jul, 2024 - Comments: 0

Line edge roughness (LER) is a variation in the width of a lithographic pattern along one edge of a structure inside a chip. Line edge roughness can be a critical variation source and defect mechanism in advanced logic and memory devices and can lead to poor device performance or even device failure. [1~3]. Deposition-etch cycling is an effective technique to reduce line edge roughness. In this... » read more

Blog Review: July 17
By Jesse Allen - 17 Jul, 2024 - Comments: 0

Cadence's Xin Mu explains the PCIe ECN Unordered IO (UIO) feature in the PCIe 6.1 specification, which defines a new wire semantic and related capabilities to enable multiple-path fabric support and helps avoid unnecessary traffic for better bandwidth and latency. Synopsys' Dana Neustadter, Gary Ruggles, and Richard Solomon highlight the latest updates in the CXL 3.1 standard, including new ... » read more

Virtual Exploration Of Novel Vertical DRAM Architectures
By Taeyon (TY) Oh - 20 Jun, 2024 - Comments: 0

In this article, we demonstrate a pathfinding technique for a novel Vertical DRAM technology. First, we identify important process parameters (defined by current semiconductor production equipment capabilities) that strongly impact yield. By using a virtual model, we then perform experimental optimization of the Vertical DRAM device across specific target ranges, to help predict and improve the... » read more

Understanding CFETs, A Next Generation Transistor Architecture
By Sam Sarkar - 23 May, 2024 - Comments: 0

Computing power has experienced exponential growth over the last 70 years. This has largely been achieved through transistor scaling. Due to a continuous reduction in the size of transistors, engineers have been able to pack more and more of them onto a single chip [1]. This has led to faster, more powerful, and more energy-efficient devices. Improvements in fabrication processes and materials,... » read more

Exploring Process Scenarios To Improve DRAM Device Performance
By Yu De Chen - 18 Apr, 2024 - Comments: 0

In the world of advanced semiconductor fabrication, creating precise device profiles (edge shapes) is an important step in achieving targeted on-chip electrical performance. For example, saddle fin profiles in a DRAM memory device must be precisely fabricated during process development in order to avoid memory performance issues. Saddle fins were introduced in DRAM devices to increase channel l... » read more

Review Of Virtual Wafer Process Modeling And Metrology For Advanced Technology Development
By Coventor - 17 Apr, 2024 - Comments: 0

Semiconductor logic and memory technology development continues to push the limits of process complexity and cost, especially as the industry migrates to the 5 nm node and beyond. Optimization of the process flow and ultimately quantifying its physical and electrical properties are critical steps in yielding mature technology. The standard build, test, and wait model of technology development ... » read more

Techniques To Identify And Correct Asymmetric Wafer Map Defects Caused By Design And Process Errors
By James Kim - 22 Feb, 2024 - Comments: 0

Asymmetries in wafer map defects are usually treated as random production hardware defects. For example, asymmetric wafer defects can be caused by particles inadvertently deposited on a wafer during any number of process steps. In this article, I want to share a different mechanism that can cause wafer defects. Namely, that these defects can be structural defects that are caused by a biased dep... » read more

Fan-Out Panel-Level Packaging Hurdles
By Anne Meixner - 24 Jan, 2024 - Comments: 0

Fan-out panel-level packaging (FOPLP) promises to significantly lower assembly costs over fan-out wafer-level packaging, providing the relevant processes for die placement, molding and redistribution layers (RDLs) formation can be scaled up with equivalent yield. There is still much work to be done before that happens. Until now, FOPLP has been adopted for devices that are manufactured in ve... » read more

Navigating Heat In Advanced Packaging
By Gregory Haley - 18 Jan, 2024 - Comments: 0

The integration of multiple heterogeneous dies in a package is pivotal for extending Moore’s Law and enhancing performance, power efficiency, and functionality, but it also is raising significant issues over how to manage the thermal load. Advanced packaging provides a way to pack more features and functions into a device, increasingly by stacking various components vertically rather than ... » read more

Developing ReRAM As Next Generation On-Chip Memory For Machine Learning, Image Processing And Other Advanced CPU Applications
By Brett Lowe - 18 Jan, 2024 - Comments: 0

In modern CPU device operation, 80% to 90% of energy consumption and timing delays are caused by the movement of data between the CPU and off-chip memory. To alleviate this performance concern, designers are adding additional on-chip memory to their CPUs. Traditionally, SRAM has been the most widely used on-chip CPU memory type. Unfortunately, SRAM is currently limited to a size of hundreds of ... » read more

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