Connecting Wafer Level Parasitic Extraction And Netlisting


The semiconductor technology simulation world is typically divided into device-level TCAD (technology CAD) and circuit-level compact modeling. Larger EDA companies provide high-level design simulation tools that perform LVS (layout vs. schematic), DRC (design rule checking), and many other software solutions that facilitate the entire design process at the most advanced technology nodes. In thi... » read more

Self-aligned Fin Cut Last Patterning Scheme for Fin Arrays of 24nm Pitch and Beyond


In 5nm FinFET technology and beyond, SRAM cell size reduction to 6 tracks is required with a fin pitch of 24nm. Fin depopulation is mandatory to enable area scaling, but it becomes challenging at small pitches. In the first part of our study, we simulate a FinFET process flow with various fin cut approaches to obtain a 3D model of a FinFET SRAM device. Layout dependent effects on silicon and pr... » read more

Improving SAQP Patterning Yield Using Virtual Fabrication And Advanced Process Control


Advanced logic scaling has created some difficult technical challenges, including a requirement for highly dense patterning. Imec recently confronted this challenge, by working toward the use of Metal 2 (M2) line patterning with a 16 nm half-pitch for their 7nm node (equivalent to a 5nm foundry node). Self-Aligned Quadruple Patterning (SAQP) was investigated as an alternative path to Extreme Ul... » read more

Virtual Fabrication And Advanced Process Control Improve Yield For SAQP Process Assessment With 16nm Half-Pitch


This paper uses Virtual Fabrication to assess the Imec 7nm node (iN7) Self-Aligned Quadruple Patterning (SAQP) integration scheme for the 16nm half-pitch Metal 2 line formation. We first present the technical challenge of obtaining defect-free M2 lines with SAQP, and then provide a solution to achieve a » read more

Making Chip Packaging Simpler


Packaging is emerging as one of the most critical elements in semiconductor design, but it's also proving difficult to master both technically and economically. The original role of packaging was simply to protect the chips inside, and there are still packages that do just that. But at advanced nodes, and with the integration of heterogeneous components built using different manufacturing pr... » read more

Everything You Need to Know about FDSOI Technology


Over the past decades, transistor feature size has continuously decreased, leading to an increase in performance and a reduction in power consumption. Consumers have reaped the benefits, with superior electronic devices that have become increasingly useful, valuable, faster and more efficient. In recent years, as transistor feature size has shrunk below 10nm, it has become progressively more di... » read more

Finding Defects In Chips With Machine Learning


Chipmakers are using more and different traditional tool types than ever to find killer defects in advanced chips, but they are also turning to complementary solutions like advanced forms of machine learning to help solve the problem. A subset of artificial intelligence (AI), machine learning has been used in computing and other fields for decades. In fact, early forms of machine learning ha... » read more

Innovative Solutions To Increase 3D NAND Flash Memory Density


In the last 10 years, 3D NAND flash memory has enabled a new generation of non-volatile solid-state storage useful in nearly every electronic device imaginable. 3D NAND can achieve data densities exceeding those of 2D NAND structures, due to the relative ease of 3D integration, even when fabricated on later generation technology nodes. 3D NAND structures contain vertical channels which orthogo... » read more

Creating Higher Density 3D NAND Structures


3D NAND flash memory has enabled a new generation of non-volatile solid-state storage useful in nearly every electronic device imaginable. 3D NAND can achieve data densities exceeding those of 2D NAND structures, even when fabricated on later generation technology nodes. The methods used to increase storage capacity come with potentially significant tradeoffs in memory storage, structural sta... » read more

Using Sensor Data To Improve Yield And Uptime


Semiconductor equipment vendors are starting to add more sensors into their tools in an effort to improve fab uptime and wafer yield, and to reduce cost of ownership and chip failures. Massive amounts of data gleaned from those tools is expected to provide far more detail than in the past about multiple types and sources of variation, including when and where that variation occurred and how,... » read more

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