A Study Of Next-Generation CFET Process Integration Options

Decision making is a critical step in semiconductor technology development. R&D semiconductor engineers must consider different design and process options early in the development of a next-generation technology. Established techniques such as Failure Mode and Effect Analysis (FMEA) can be used to select among the most promising design and process choices. Once specific design and process m... » read more

A Benchmark Study Of Complementary-Field Effect Transistor (CFET) Process Integration Options

Sub-5 nm logic nodes will require an extremely high level of innovation to overcome the inherent real-estate limitations at this increased device density. One approach to increasing device density is to look at the vertical device dimension (z-direction), and stack devices on top of each other instead of conventionally side-by-side. [1] The fabrication of a Complementary-Field Effect Transistor... » read more

Making Random Variation Less Random

The economics for random variation are changing, particularly at advanced nodes and in complex packaging schemes. Random variation always will exist in semiconductor manufacturing processes, but much of what is called random has a traceable root cause. The reason it is classified as random is that it is expensive to track down all of the various quirks in a complex manufacturing process or i... » read more

Week In Review: Manufacturing, Test

Chipmakers The semiconductor capital spending race continues to escalate in the leading-edge logic space. Intel and Samsung have separately announced big capital spending plans in 2019. Intel’s latest CapEx budget is $15.5 billion in 2019, while Samsung’s CapEx is slated for $16.204 billion for the year, according to KeyBanc Capital Markets. Now, TSMC is raising the stakes. TSMC this... » read more

Advances In 3D CMOS Image Sensors Optical Modeling: Combining Realistic Morphologies With FDTD

This paper describes an innovative methodology to investigate the relationship between device morphology and the optical performance of CMOS image sensors. By coupling a FDTD-based 3D Maxwell solver with silicon-accurate process modeling software, we have been able to analyze the sensitivity of image sensor quantum efficiency with respect to statistical variations in nm-scale device topology. A... » read more

Influence Of SiGe On Parasitic Parameters in PMOS

In this paper, simulation-based design-technology co-optimization (DTCO) is carried out using the Coventor SEMulator3D virtual fabrication platform with its integrated electrical analysis capabilities [1]. In our study, process modeling is used to predict the sensitivity of FinFET device performance to changes in a silicon germanium epitaxial process. The simulated process is a gate-last flow p... » read more

How FinFET Device Performance Is Affected By Epitaxial Process Variations

By Shih-Hao (Jacky) Huang and Yu De Chen As the need to scale transistors to ever-smaller sizes continues to press on technology designers, the impact of parasitic resistance and capacitance can approach or even outpace other aspects of transistor performance, such as fringing capacitance or source drain resistance. The total resistance in a device is comprised of two components: internal re... » read more

Effects Of A Random Process Variation On The Transfer Characteristics Of A Fundamental Photonic Integrated Circuit Component

Silicon photonics is rapidly emerging as a promising technology to enable higher bandwidth, lower energy, and lower latency communication and information processing, and other applications. In silicon photonics, existing CMOS manufacturing infrastructure and techniques are leveraged. However, a key challenge for silicon photonics is the lack of mature models that take into account known CMOS pr... » read more

Advanced Patterning Techniques For 3D NAND Devices

By Yu De Chen and Jacky Huang Driven by Moore’s law, memory and logic semiconductor manufacturers pursue higher transistor density to improve product cost and performance [1]. In NAND Flash technologies, this has led to the market dominance of 3D structures instead of 2D planar devices. Device density can be linearly increased by increasing stack layer counts in a 3D NAND device [2]. At th... » read more

Backside Power Delivery as a Scaling Knob for Future Systems

Standard cell track height scaling provides us with sufficient area scaling at the standard cell library level. The efficiency of this technique and the complexities involved with this scaling method have been discussed in detail. However, the area benefits of standard cell track height scaling diminish when we consider the complexities of incorporating on-chip power grid into the DTCO explorat... » read more

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