Design Rule Complexity Rising


Variation, edge placement error, and a variety of other issues at new process geometries are forcing chipmakers and EDA vendors to confront a growing volume of increasingly complex, and sometimes interconnected design rules to ensure chips are manufacturable. The number of rules has increased to the point where it's impossible to manually keep track of all of them, and that has led to new pr... » read more

Modeling Semiconductor Process Variation


3D semiconductors, 3D NAND Flash, FinFETS and other advanced devices are bringing tremendous opportunities to the semiconductor industry. Unfortunately, these devices are also bringing new design, process and production problems. Process variability has been a major contributor to production delays as feature sizes have decreased and process complexity has increased. Virtual fabrication is a co... » read more

What Happened To Nanoimprint Litho?


Nanoimprint lithography (NIL) is re-emerging amid an explosion of new applications in the market. Canon, EV Group, Nanonex, Suss and others continue to develop and ship NIL systems for a range of markets. NIL is different than conventional lithography and resembles a stamping process. Initially, a lithographic system forms a pattern on a template based on a pre-defined design. Then, a separa... » read more

Self-Aligned Block And Fully Self-Aligned Via For iN5 Metal 2 Self-Aligned Quadruple Patterning


This paper assesses Self-Aligned Block (SAB) and Fully Self-Aligned Via (FSAV) approaches to patterning using a iN5 (imec node 5 nm) vehicle and Metal 2 Self-Aligned Quadruple Patterning. We analyze SAB printability in the lithography process using process optimization, and demonstrate the effect of SAB on patterning yield for a (8 M2 lines x 6 M1 lines x 6 Via) structure. We show that FSAV, co... » read more

Improving Patterning Yield At The 5nm Semiconductor Node


Engineering decisions are always data-driven. As scientists, we only believe in facts and not in intuition or feelings. At the manufacturing stage, the semiconductor industry is eager to provide data and facts to engineers based upon metrics such as the quantity of wafers produced per hour and sites/devices tested on each of those wafers. The massive quantity of data generated in semiconduct... » read more

DSA Re-Enters Litho Picture


By Mark LaPedus and Ed Sperling Directed self-assembly (DSA) is moving back onto the patterning radar screen amid ongoing challenges in lithography. Intel continues to have a keen interest in [gettech id="31046" t_name="DSA"], while other chipmakers are taking another hard look at the technology, according to multiple industry sources. DSA isn't like a traditional [getkc id="80" kc_name="... » read more

The Next 5 Years Of Chip Technology


Semiconductor Engineering sat down to discuss the future of scaling, the impact of variation, and the introduction of new materials and technologies, with Rick Gottscho, CTO of Lam Research; Mark Dougherty, vice president of advanced module engineering at GlobalFoundries; David Shortt, technical fellow at KLA-Tencor; Gary Zhang, vice president of computational litho products at ASML; and Shay... » read more

The Week In Review: Manufacturing


Fab tools Samsung Electronics has broken ground on a new extreme ultraviolet (EUV) lithography facility in Hwaseong, South Korea. The new EUV facility is expected to be completed within the second half of 2019 with production slated for 2020. The initial investment in the new EUV line is projected to reach $6 billion by 2020. Imec and Cadence Design Systems have collaborated on the develop... » read more

Blog Review: Feb. 28


Mentor's Matthew Ballance explains just what the portable stimulus standard makes portable. Cadence's Dave Pursley considers why high-level synthesis is a good fit for cutting-edge machine learning designs. Synopsys' Melissa Kirschner notes that the growing number of IoT devices means new opportunities for one-time programmable NVM. Applied's Mike Rosa considers the pros and cons of 5G... » read more

FD-SOI Adoption Expands


Fully depleted silicon-on-insulator (FD-SOI) is gaining ground across a number of new markets, ranging from IoT to automotive to machine learning, and diverging sharply from its original position as a less costly alternative to finFET-based designs. For years, [getkc id="220" kc_name="FD-SOI"] has been viewed as an either/or solution targeted at the same markets as bulk [gettech id="31093" c... » read more

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