Author's Latest Posts


Understanding Within-Wafer Variations: A Virtual Fabrication Approach


One of the unavoidable aspects of chip manufacturing is that some dies on a wafer perform differently than others, even though they were made together on the same wafer. This blog dives into that mystery and provides a way to predict and fix these issues. Imagine baking cookies. If your oven has hot and cold spots, some cookies will be perfect; others burnt. That’s what happens in chip man... » read more

The Other Side Of The Wafer: Transistor Channel Stress In Backside Power Delivery Networks


As transistor scaling has moved to the angstrom era (18A, 14A, etc.), the issues of interconnect resistance (IR), IR drop, and power loss are becoming more severe. Traditionally, signal lines and power lines are fabricated on the same side of the wafer as the active device. But fabricating everything on one side of the wafer can create a shortage of space and resources at the interconnect la... » read more

Understanding CFETs, A Next Generation Transistor Architecture


Computing power has experienced exponential growth over the last 70 years. This has largely been achieved through transistor scaling. Due to a continuous reduction in the size of transistors, engineers have been able to pack more and more of them onto a single chip [1]. This has led to faster, more powerful, and more energy-efficient devices. Improvements in fabrication processes and materials,... » read more