Challenges And Solutions For Silicon Wafer Bevel Defects During 3D NAND Flash Manufacturing


As semiconductor technology scales down in size, process integration complexity and defects are increasing in 3D NAND flash, partially due to larger stack deposits and thickness variability between the wafer center and the wafer edge. Industry participants are working to reduce defect density at the wafer edge to improve overall wafer yield. Attention has focused on common wafer bevel defects s... » read more

3D NAND Race Faces Huge Tech And Cost Challenges


Amid the ongoing memory downturn, 3D NAND suppliers continue to race each other to the next technology generations with several challenges and a possible shakeout ahead. Micron, Samsung, SK Hynix and the Toshiba-Western Digital duo are developing 3D NAND products at the next nodes on the roadmap, but the status of two others, Intel and China’s Yangtze Memory Technologies Co. (YMTC), is les... » read more

Blog Review: April 24


Rambus' Steven Woo checks out changes in the hardware used for neural network training and the importance of co-design of hardware and software. Cadence's Meera Collier makes an argument for why vehicle sensors watching the driver could prevent some distraction and fatigue-related crashes. Synopsys' Dan Lyon and Garrett Sipple point to some best practices for how to deal with a changing t... » read more

Controlling IC Manufacturing Processes For Yield


Equipment and tools vendors are starting to focus on data as a means of improving yield, adding more sensors and analysis capabilities into the manufacturing flow to circumvent problems in real time. How much this will impact the cost of developing complex chips at leading-edge nodes, and in 2.5D and 3D-IC packages, remains to be seen. But the race to both generate data during manufacturing ... » read more

Connecting Wafer-Level Parasitic Extraction And Netlisting


The semiconductor technology simulation world is typically divided into device-level TCAD (technology CAD) and circuit-level compact modeling. Larger EDA companies provide high-level design simulation tools that perform LVS (layout vs. schematic), DRC (design rule checking), and many other software solutions that facilitate the entire design process at the most advanced technology nodes. In thi... » read more

Self-aligned Fin Cut Last Patterning Scheme for Fin Arrays of 24nm Pitch and Beyond


In 5nm FinFET technology and beyond, SRAM cell size reduction to 6 tracks is required with a fin pitch of 24nm. Fin depopulation is mandatory to enable area scaling, but it becomes challenging at small pitches. In the first part of our study, we simulate a FinFET process flow with various fin cut approaches to obtain a 3D model of a FinFET SRAM device. Layout dependent effects on silicon and pr... » read more

Improving SAQP Patterning Yield Using Virtual Fabrication And Advanced Process Control


Advanced logic scaling has created some difficult technical challenges, including a requirement for highly dense patterning. Imec recently confronted this challenge, by working toward the use of Metal 2 (M2) line patterning with a 16 nm half-pitch for their 7nm node (equivalent to a 5nm foundry node). Self-Aligned Quadruple Patterning (SAQP) was investigated as an alternative path to Extreme Ul... » read more

Virtual Fabrication And Advanced Process Control Improve Yield For SAQP Process Assessment With 16nm Half-Pitch


This paper uses Virtual Fabrication to assess the Imec 7nm node (iN7) Self-Aligned Quadruple Patterning (SAQP) integration scheme for the 16nm half-pitch Metal 2 line formation. We first present the technical challenge of obtaining defect-free M2 lines with SAQP, and then provide a solution to achieve a » read more

Making Chip Packaging Simpler


Packaging is emerging as one of the most critical elements in semiconductor design, but it's also proving difficult to master both technically and economically. The original role of packaging was simply to protect the chips inside, and there are still packages that do just that. But at advanced nodes, and with the integration of heterogeneous components built using different manufacturing pr... » read more

Everything You Need to Know about FDSOI Technology


Over the past decades, transistor feature size has continuously decreased, leading to an increase in performance and a reduction in power consumption. Consumers have reaped the benefits, with superior electronic devices that have become increasingly useful, valuable, faster and more efficient. In recent years, as transistor feature size has shrunk below 10nm, it has become progressively more di... » read more

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