Author's Latest Posts


Using Virtual Twins To Accelerate The Transition From Layout To Semiconductor Manufacturing


Standard electronic design automation (EDA) tools can be used to produce a semiconductor layout, which can be used to manufacture a device with targeted performance specifications. Unfortunately, designers have learned from experience that process capabilities on semiconductor manufacturing equipment can limit device yield and performance of any idealized device layout. Even though every... » read more

Using Dummy Patterning To Solve Etch Uniformity Problems


Semiconductor devices are made up of hundreds of thin layers of materials stacked by multiple deposition and etch processes. Process engineers need to design the best combination of deposition and etch processes to ensure uniformity across an entire chip area and across the silicon wafer. Uniformity is the most common and critical parameter that is monitored in semiconductor fabrication, especi... » read more

Techniques To Identify And Correct Asymmetric Wafer Map Defects Caused By Design And Process Errors


Asymmetries in wafer map defects are usually treated as random production hardware defects. For example, asymmetric wafer defects can be caused by particles inadvertently deposited on a wafer during any number of process steps. In this article, I want to share a different mechanism that can cause wafer defects. Namely, that these defects can be structural defects that are caused by a biased dep... » read more