tag: process modeling

Why 3D NAND Layers Bend (And How To Prevent It)
By Brett Lowe - 21 Aug, 2025 - Comments: 0

3D NAND flash memory is built by vertically stacking multiple alternating layers (tiers) of silicon nitride (SiN) and oxide (TEOS) on top of each other. A major challenge in producing multilayered 3D NAND devices is tier bending and tier collapse. These undesirable conditions can be caused by a combination of factors. Using the virtual Design of Experiment (DOE) capabilities in SEMulator... » read more

Semiconductor Virtual Fabrication And Its Applications
By Qingpeng Wang - 24 Jul, 2025 - Comments: 0

Semiverse Solutions, particularly SEMulator3D, can enhance semiconductor engineering in several ways. SEMulator3D is a software platform for semiconductor process modeling and virtual fabrication.1 Prototyping and visualization: Virtual fabrication aids in understanding and visualizing complex semiconductor structures in three dimensions, facilitating better design and prototyping. Unit... » read more

Examining Mechanical Deformation In Advanced Logic Devices To Enhance Yield
By Sandy Wen - 19 Jun, 2025 - Comments: 0

By Sandy Wen and Jacky Huang As dimensions shrink and aspect ratios increase in advanced logic devices, it is increasingly important to reduce structural device variation. Structural device variations can be a proxy for device yield. These variations might include critical dimension (CD), gate CD, gate height, and proximity between neighboring vias. One contributor to structural device v... » read more

TCAD-Based AI Models For Modern Fab Workflows
By Saurabh Suryavanshi - 20 Mar, 2025 - Comments: 0

The relentless pace of semiconductor development continues unabated. Despite the slowdown in Moore’s law, feature sizes continue to shrink as new geometries come online. Constant innovations in both fab processes and device design offer new opportunities but present new challenges. As in so many other areas of electronics, artificial intelligence (AI) is starting to play a significant role. ... » read more

Improving DRAM Performance Using Dual Work-Function Metal Gate (DWMG) Structures
By Daebin Yim - 20 Mar, 2025 - Comments: 0

Dynamic Random Access Memory (DRAM) serves as the backbone of modern computing, enabling devices ranging from smartphones to high-performance servers. As the demand accelerates for higher density and lower power consumption in memory devices, innovation in reducing DRAM leakage currents and enhancing performance becomes essential. One significant challenge in scaling DRAM technology is gate-... » read more

Mechanical Stress In Semiconductor Development
By Ivan Chakarov - 20 Feb, 2025 - Comments: 0

With the semiconductor industry moving toward 3D DRAM, 3D logic architectures, and 1000+ layer 3D NAND stacks,1 mechanical failures may become more common. Due to the complexity of these structures, mechanical stress from materials processing has the potential to significantly impact yield. 3D processing techniques (etching, deposition, and related chemistries), as well as material property de... » read more

Using Dummy Patterning To Solve Etch Uniformity Problems
By James Kim - 21 Nov, 2024 - Comments: 0

Semiconductor devices are made up of hundreds of thin layers of materials stacked by multiple deposition and etch processes. Process engineers need to design the best combination of deposition and etch processes to ensure uniformity across an entire chip area and across the silicon wafer. Uniformity is the most common and critical parameter that is monitored in semiconductor fabrication, especi... » read more

Metal-Oxide-Metal Capacitor Simulation And Modeling By Virtual Fabrication
By Qingpeng Wang - 24 Oct, 2024 - Comments: 0

Metal-Oxide-Metal (MOM) capacitors are passive radio frequency (RF) capacitive devices that are a common component in semiconductor logic chips [1]. A SPICE model of a MOM capacitor is typically used by designers during the design and performance evaluation of logic chip RF circuitry. Traditionally, it may take at least 3 months from the completion of the design layout, wafer fabrication, final... » read more

Reducing Transistor Capacitance At The 5nm Node Using A Source/Drain Contact Recess
By Pradeep Nanja - 19 Sep, 2024 - Comments: 0

In logic devices such as FinFETs (field-effect transistors), metal gate parasitic capacitance can negatively impact electrical performance. One potential way to reduce this parasitic capacitance is to add a source/drain contact (CT) recess step when building the source/drain metal structure. However, this additional structure can potentially increase the source/drain to via resistance. Using... » read more

Improving Line Edge Roughness Using Virtual Fabrication
By Qingpeng Wang - 23 Jul, 2024 - Comments: 0

Line edge roughness (LER) is a variation in the width of a lithographic pattern along one edge of a structure inside a chip. Line edge roughness can be a critical variation source and defect mechanism in advanced logic and memory devices and can lead to poor device performance or even device failure. [1~3]. Deposition-etch cycling is an effective technique to reduce line edge roughness. In this... » read more

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