Why 3D NAND Layers Bend (And How To Prevent It)

3D NAND flash memory is built by vertically stacking multiple alternating layers (tiers) of silicon nitride (SiN) and oxide (TEOS) on top of each other.

A major challenge in producing multilayered 3D NAND devices is tier bending and tier collapse. These undesirable conditions can be caused by a combination of factors.

Using the virtual Design of Experiment (DOE) capabilities in SEMulator3D, we were able to measure displacement of the tier layers under varying experimental conditions. We discovered that the greatest process and yield improvements can be delivered by reducing and matching the compressive stress (force per unit area) and axial strain of SiN and oxide layers.

Making memory

Higher memory densities can be achieved with 3D NAND by increasing the number of metal and oxide layers. In current high-volume manufacturing, the alternating stack has exceeded 200 layers in height and will soon exceed 300 layers.^1,2

Manufacturing 3D NAND tier stacks relies on the deposition of alternating layers of silicon nitride (SiN) and oxide (TEOS). These materials are layered in a staircase pattern to provide access to the memory wordline in the staircase region. High-aspect ratio contacts are then etched through the tier stack to contact the under-array transistors. The tier stack is subsequently separated into memory blocks by a high-aspect ratio slit etch.

The SiN tiers are then selectively removed and replaced with conductive metal. Before the SiN is replaced, a classical oxide cantilever is formed from the contact (supported end) to the slit (unsupported end) (Figure 1a).

Fig. 1a: A cantilever is formed from the contact (supported end on the left) to the slit (unsupported end on the right). Fig. 1b: SEM image of tier collapse.³

A major challenge in 3D NAND design and manufacturing is tier bending and tier collapse (Figure 1b). Tier collapse of the oxide cantilever can be caused by a combination of factors: intrinsic stress and strain of the SiN and oxide, surface tension and wetting surface area during the SiN removal process, and length of the cantilever.

As the number of layers in the stack increases, the span of the cantilever lengthens in the deeper layers of the stack due to tapering of the slit bottom profile. The cantilever length increases from 550 nm to 700 nm when going from a 200-layer 3D NAND structure to a 300-layer structure and using high aspect ratio contact and slit etches with a constant sidewall slope of 89° (Figure 2).

Fig. 2: Cantilever length comparison of 200-layer 3D NAND to 300-layer 3D NAND. The sidewall slope of the contact and slit etches is 89°.

The Semiverse Solutions team conducted a study of tier bending and tier collapse using the stress analysis capabilities of the SEMulator3D process modeling platform. Physical deformation of the tiers, caused by stress evolution during device manufacturing, ultimately creates voids and missing metal during the replacement metal gate process steps.

Contributing factors

A first virtual study (Design of Experiments, or DOE) was executed to determine the most important factors that contribute to tier bending and tier collapse. The factors studied included material intrinsic stress (s) and tensile modulus (Ey, or Young’s Modulus) of the tier layers, tier layer thickness, and cantilever length.

The virtual DOE was completed, and model cross-section images were generated to display the impact of stress evolution after the metal replacement step (Figure 3). Measurements of the separation of oxide Tiers 2 and 3 were taken at the unsupported end of the cantilever using virtual metrology.

The Ey of the SiN (as trisilicon tetranitride, or Si₃N₄) varied from 70 to 256 GPa using two levels of thickness, 25 nm and 30 nm. The cantilever length varied from 550 nm to 700 nm. Two levels of TEOS oxide thickness were used in the study (20 nm and 25 nm) and the TEOS oxide Ey was fixed at 70 GPa.

Study results

The results indicate that at both oxide thicknesses, and when SiN Ey = 70 GPa, there is very little displacement in the separation of the oxide tiers away from the original values.

At a value of SiN Ey = 125 GPa, the effects of stress on the 3D NAND device were apparent.

• There was a complete tier collapse and significant metal voiding at a cantilever length of 700 nm when using SiN and oxide thicknesses of 30 nm and 20 nm, respectively.
• Increasing the oxide thickness to 25 nm (without other changes) had less effect but still showed significant displacement and metal voiding.

At a value of SiN Ey = 256 GPa, there was total stress-based displacement in all experimental conditions and widespread occurrence of missing metal.

Figure 3 provides a graphical summary of the Virtual DOE results. The most important variables that impacted device stress and displacement were SiN Ey and oxide thickness. These values should be reduced and matched.

The DOE also highlights secondary changes that can be made to improve yield, including shortening the cantilever length and increasing the thickness of the oxide.

Fig. 3: Virtual DOE results. Separation of the oxide Tiers 2 and 3, measured at the unsupported end of the cantilever, versus silicon nitride (Si₃N₄) thickness, Young’s Modulus (Ey), and TEOS oxide thickness. Tier-bending images are shown at a cantilever length equal to 600 nm.

Second study

Next, we completed a second virtual DOE that compared the separation of the tiers versus different values of  Si₃N₄, Ey, and SiN intrinsic stress (Figure 4).

Fig. 4: Virtual DOE results. Separation of the oxide Tiers 2 and 3, measured at the unsupported end of the cantilever versus silicon nitride (Si₃N₄), Young’s Modulus (Ey), and Si₃N₄ intrinsic stress.

The response variable is the separation of the oxide Tiers 2 and 3, measured using virtual metrology at the unsupported end of the cantilever. The Ey of the SiN varied from 70 to 256 GPa when using two levels of SiN intrinsic stress: -1,000 MPa and 1,000 MPa. The TEOS oxide stress and modulus were fixed.

The results indicate that compressive SiN has a wider displacement latitude (greater stress-based displacement) than tensile SiN.

Conclusion

As shown in this article, the SEMulator3D Stress Analysis package can analyze the impact of stress on device deformation and yield, without resorting to expensive and time-consuming silicon-based testing. These capabilities can be used to accelerate process development and help engineers make better decisions when performing in-fab experiments on live silicon.

References

1. K. Heyman, “Is There a Limit to the Number of Layers in 3D-NAND?” Semiconductor Engineering, 10/24/2022. https://semiengineering.com/is-there-a-limit-to-the-number-of-layers-in-3d-nand/.
2. R. Smith, “Micron’s 232 Layer NAND Now Shipping: 1Tbit, 6-Planes Dies with 50% More I/O Bandwidth.” AnandTech, 7/26/2022. https://www.anandtech.com/show/17509/microns-232-layer-nand-now-shipping.
3. R. Klein, “3D NAND Vertical Scaling-Structural and Metallization Challenges, Related to Word-Line Processing.” 2023 WISH Conference Proceedings, 10/12/2023.