Brett Lowe

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Brett Lowe is a senior manager in the Semiconductor Process & Integration group at Semiverse Solutions, Lam Research. He has worked in semiconductor technology development for more than 35 years. He began his career at Philips Semiconductors, where he worked in manufacturing and process development as a process engineer in the photolithography, dry etch and wet process areas. He then spent eight years at Zilog, working on unit process development. Later, Brett joined Micron Technology, where he worked in DRAM and 3D NAND process development and integration. At Coventor, his focus is on supporting the company’s customers in their 3D semiconductor process modeling and technology development requirements.

Author's Latest Posts

Process Model Precision: Calibrating For Accurate Predictions Of FinFET Device Profiles

By Brett Lowe - 19 Mar, 2026 - Comments: 0

In modern semiconductor process integration, rapid and well-informed path finding is essential for on-time product release. Virtual Design of Engineering (DOE) and predictive modeling can expose integration risks early; however, their value depends on accurate process models calibrated to real fab behavior.1 Reliable prediction requires strong correlations between model inputs and measurable... » read more

Why 3D NAND Layers Bend (And How To Prevent It)

By Brett Lowe - 21 Aug, 2025 - Comments: 0

3D NAND flash memory is built by vertically stacking multiple alternating layers (tiers) of silicon nitride (SiN) and oxide (TEOS) on top of each other. A major challenge in producing multilayered 3D NAND devices is tier bending and tier collapse. These undesirable conditions can be caused by a combination of factors. Using the virtual Design of Experiment (DOE) capabilities in SEMulator... » read more

Developing ReRAM As Next Generation On-Chip Memory For Machine Learning, Image Processing And Other Advanced CPU Applications

By Brett Lowe - 18 Jan, 2024 - Comments: 0

In modern CPU device operation, 80% to 90% of energy consumption and timing delays are caused by the movement of data between the CPU and off-chip memory. To alleviate this performance concern, designers are adding additional on-chip memory to their CPUs. Traditionally, SRAM has been the most widely used on-chip CPU memory type. Unfortunately, SRAM is currently limited to a size of hundreds of ... » read more

3D NAND Virtual Process Troubleshooting And Investigation

By Brett Lowe - 18 Aug, 2022 - Comments: 0

Modern semiconductor processes are extremely complicated and involve thousands of interacting individual process steps. During the development of these process steps, roadblocks and barriers are often encountered in the form of unanticipated negative interactions between upstream and downstream process modules. These barriers can create a long delay in the development cycle and increase costs. ... » read more