Developing ReRAM As Next Generation On-Chip Memory For Machine Learning, Image Processing And Other Advanced CPU Applications

In modern CPU device operation, 80% to 90% of energy consumption and timing delays are caused by the movement of data between the CPU and off-chip memory. To alleviate this performance concern, designers are adding additional on-chip memory to their CPUs. Traditionally, SRAM has been the most widely used on-chip CPU memory type. Unfortunately, SRAM is currently limited to a size of hundreds of megabytes. This on-chip memory constraint may be insufficient for leading edge applications.

Future CPU applications, such as AI Language Model programming and image processing for 8K UHD video, will require I/O memory access bandwidth in the range of 10 terabytes/sec. To meet these bandwidth requirements, on-chip CPU memory will need to be greater than 1 terabyte in size. An SRAM alternative may be needed to meet these future on-chip memory requirements. One possible solution to this problem would be to use Resistive Random Access Memory (ReRAM). [1,2,3]

A ReRAM device is a non-volatile memory cell that contains memristor materials. These materials act as a dielectric insulator. When a sufficiently high voltage is applied a conduction path is formed. Typical memory materials used as memristors include HfO₂, Ta₂O₅, and TiO₂. [4] The resistive state of the memory cell can be read using electronic circuits to determine if the memory cell is programmed or erased, thus identifying the state of the memory bit. ReRAM memory cells can be stacked vertically, like 3D-NAND architecture, to increase the storage density.

In this article, SEMulator3D Virtual Fabrication will be used for process pathfinding and visualization of potential 3D ReRAM architectures. We will estimate cell resistance as a function of memory cell shape, along with the Id-Vg performance of the embedded channel transistor in a ReRAM device.

A 3D ReRAM model is shown in figure 1. The device has 64 layers of wordlines (WL) with pillars placed in a hexagonal spaced array. The wordlines are formed with alternating layers of metallic conductors and oxide dielectric. The pillars are etched through the WL and then a thin layer of memory material is deposited onto the sidewalls of the pillars. The memory material is removed from the bottom and top of the pillars, leaving only the material on the sidewalls of the pillar. The pillars are then filled with refractory metal and tungsten.

Under the array layers are contacts and metal interconnect to the source, drain and gates of gate-all-around field effect transistors (GAA FET). The transistor drain connects to the memory array pillar and combines with the WL circuit to provide function to each memory cell.

The memory cell consists of two metal electrodes: the metallic conductor wordline and a refractory metal electrode (figure 2). During virtual process simulation of this device, we will use process variables to set and reset the memristor. A deliberately applied voltage will create microscopic conductive paths called conductive filaments. When electrical signals of different polarities are applied, the charged ions inside the memristor move to form (set) or dissolve (reset) the conductive filament.

The conductive filament resistance varies at different program voltages. The low resistance state is in the range of 10k ohm (set) and the high resistance state is in the range of 1M ohm (reset). [5] We developed a virtual model to demonstrate the switching resistances of a 3D ReRAM device, with results displayed in figure 3. The high resistive state of the memristor is approximately 100 times higher resistance than the low resistive state.

A virtual Design of Experiments (DOE) was then executed to better understand the correlation between the memory cell resistance ratio and the size and shape of the memory cell. The variables of the experiment were pillar CD, WL thickness and memristor thickness. Analysis of the DOE results indicate that pillar CD and thickness of the memristor drove the most significant response. Figure 4 displays a contour plot of the memory cell resistance ratio versus these two variables. There was a 3X change in the memory cell resistance for high values of pillar radius and memristor thickness. The differences in shape of the memory cell across the studied range will not affect the ability to read the memory states of the memristor but could affect the ability to discern program states in a multibit per cell device.

The memristor can be programmed using a current < 0.10 uA and a voltage < 0.5V. These voltage and current settings will allow memristors (ReRAM memory) to easily integrate as on-chip memory into advanced logic devices. SEMulator3D device simulation has previously demonstrated that a GAA FET under-array transistor should be able to drive the voltage and current required by the set and reset states of a memristor memory cell. [6]

Two major problems of modern CPU devices are energy consumption and delay time caused by data movement between the CPU and off-chip memory. Increasing the size of on-chip memory may solve these problems. In this study, we have used SEMulator3D to investigate the integration of an SRAM alternative (ReRAM) for CPU for on-chip memory. We used a virtual model to better understand process steps and potential layout problems for individual memristor cells. We also executed studies to examine the set and reset states of the memristor and the effect of device dimensions (memory cell shape and size) on wordline resistance. We highlighted that ReRAM on-board memory can be integrated with advanced logic, by using a GAA pFET transistor electrical output to set and reset the memristor cells. These results confirm that Resistive Random Access Memory (ReRAM) is a promising alternative to on-board SRAM memory for future high-bandwidth logic applications.

References

1. Lanza, Mario (2014). “A Review on Resistive Switching in High-k Dielectrics: A Nanoscale Point of View Using Conductive Atomic Force Microscope”. Materials, vol. 7, issue 3, pp. 2155-2182, doi:10.3390/ma7032155.
2. N. Sedghi, et al, “The role of nitrogen doping in ALD Ta2O5 and its influence on multilevel cell switching in RRAM”, March 2017, Applied Physics Letters, DOI:10.1063/1.4978033
3. Y. Bai, Et Al, “Study of Multi-level Characteristics for 3D Vertical Resistive Switching Memory” Scientific Reports volume 4, Article number: 5780 (2014)
4. Chen, Y. C., Sarkar, S., Gibbs, J. G., Huang, Y., Lee, J. C., Lin, C. C., & Lin, C. H. (2022). “Nano Helical-Shaped Dual-Functional Resistive Memory for Low-Power Crossbar Array Application.”, ACS Applied Engineering Materials, 1(1), 252-257.
5. Y. Wu, et al, “Nanometer-Scale HfOx RRAM”, IEEE Electron Device Letters, Volume: 34, Issue: 8, August 2013), doi:10.1109/LED.2013.2265404
6. V. Sreenivasulu, et al, “Circuit Analysis and Optimization of GAA Nanowire FET Towards Low Power and High Switching”, November 11, 2021, Computer Science, doi:10.1007/s12633-022-01777-6.