tag: virtual fabrication

Process Variation In The Era Of Scaling: Improving Uniformity With Dummy Fill
By HJ Kim - 21 May, 2026 - Comments: 0

As semiconductor patterning continues to scale, even small layout nonuniformities can lead to noticeably different process outcomes. Real chip layouts contain a mix of dense regions, large open regions, and isolated features. As a result, the etch process encounters different “local environments” across the wafer. Even with the same process settings (or recipe), some areas may etch mo... » read more

Unraveling DRAM SAQP Process Complexity With Monte Carlo Virtual Fabrication
By Swapnil Kailash More - 16 Apr, 2026 - Comments: 0

By Swapnil Kailash More and Roopa Hegde As DRAM technologies scale to increasingly tighter pitches, the patterning requirements exceed the limits of conventional single-exposure DUV lithography. In advanced nodes such as D1b (1-beta), active-area (AA) pitches fall in the range of 22 to 26 nm, well below the capability of single patterning. To achieve these sub-lithographic dimensions, advan... » read more

Process Model Precision: Calibrating For Accurate Predictions Of FinFET Device Profiles
By Brett Lowe - 19 Mar, 2026 - Comments: 0

In modern semiconductor process integration, rapid and well-informed path finding is essential for on-time product release. Virtual Design of Engineering (DOE) and predictive modeling can expose integration risks early; however, their value depends on accurate process models calibrated to real fab behavior.1 Reliable prediction requires strong correlations between model inputs and measurable... » read more

Understanding Within-Wafer Variations: A Virtual Fabrication Approach
By Sam Sarkar - 19 Feb, 2026 - Comments: 0

One of the unavoidable aspects of chip manufacturing is that some dies on a wafer perform differently than others, even though they were made together on the same wafer. This blog dives into that mystery and provides a way to predict and fix these issues. Imagine baking cookies. If your oven has hot and cold spots, some cookies will be perfect; others burnt. That’s what happens in chip man... » read more

Minimizing Voltage Loss And Improving Yield In Advanced GAA Chips
By Qingpeng Wang - 18 Dec, 2025 - Comments: 0

The problem: As metal pitch scaling shrinks to support the next generation of logic devices, the IR (or voltage) drop from conventional frontside connections has become a major challenge [1,2]. As electricity travels through a chip’s metal wiring, some voltage gets lost because wires have resistance. If the voltage drops too much, the chip’s transistors can’t get enough power and ... » read more

Overcoming BEOL Patterning Challenges At The 3nm Node
By Assawer Soussou - 20 Nov, 2025 - Comments: 0

As complementary metal-oxide semiconductor (CMOS) area shrinks 50% from one node to the next, interconnect critical dimensions (CD) and pitch (or spacing) are under tight demands. At the N3 node, where metal pitch dimensions must be at or below 18 nm,1,2 one of the main interconnect challenges is securing sufficient process margins for CD and edge placement error (EPE). Achieving the... » read more

Using Virtual Twins To Accelerate The Transition From Layout To Semiconductor Manufacturing
By James Kim - 27 Oct, 2025 - Comments: 0

Standard electronic design automation (EDA) tools can be used to produce a semiconductor layout, which can be used to manufacture a device with targeted performance specifications. Unfortunately, designers have learned from experience that process capabilities on semiconductor manufacturing equipment can limit device yield and performance of any idealized device layout. Even though every... » read more

Charting The Frontiers Of Photomask Technology And Extreme Ultraviolet Lithography
By Travis Brist - 23 Oct, 2025 - Comments: 0

The enormous computing demands of AI and high-performance computing (HPC) applications are putting intense pressure on every aspect of chip development. Challenges arise during architecture, design, and verification, persist through the manufacturing process, and extend to post-silicon lifecycle management as chips are deployed in the field. Lithography, the fabrication step of shining light... » read more

Breaking The Copper Bottleneck With Molybdenum Hybrid Metallization
By Taeyeon Oh - 18 Sep, 2025 - Comments: 0

Scaling the back end of line (BEOL) in advanced semiconductor logic devices is a major challenge. Metal lines and via filling in BEOL have historically used copper (Cu) as the electrical conductor. But as device dimensions shrink, Cu use has become problematic. The small critical dimensions (CD) of the Cu metal lines and vias in the latest BEOL structures have created an increase in resistance,... » read more

Why 3D NAND Layers Bend (And How To Prevent It)
By Brett Lowe - 21 Aug, 2025 - Comments: 0

3D NAND flash memory is built by vertically stacking multiple alternating layers (tiers) of silicon nitride (SiN) and oxide (TEOS) on top of each other. A major challenge in producing multilayered 3D NAND devices is tier bending and tier collapse. These undesirable conditions can be caused by a combination of factors. Using the virtual Design of Experiment (DOE) capabilities in SEMulator... » read more

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