tag: 3D NAND

FeFETs With Laminated Gate Stacks For Radiation Resilience in Vertical NAND (Georgia Tech)
By Technical Paper Link - 10 Mar, 2026 - Comments: 0

A new technical paper, "Enabling Radiation Hardness in Solid-State NAND Storage Utilizing a Laminated Ferroelectric Stack," was published by researchers at Georgia Tech. Abstract "NAND flash forms the core of modern solid-state storage, which is critical for data-intensive AI applications, yet charge-trap NAND suffers rapid threshold-voltage (Vth) degradation under ionizing radiation, causi... » read more

Making Hybrid Bonding Better
By Laura Peters - 02 Mar, 2026 - Comments: 0

Key Takeaways Fab processes are optimizing for cleanliness, planarity, and high bond quality. Nanotwinned copper and SiCN PVD enable lower anneal and deposition temperatures for HBM. A thin, protective layer helps preserve the Cu/dielectric during aggressive processes. The future of semiconductor manufacturing is no longer dependent just on shrinking features. Instead, chipm... » read more

Cryogenic Etch: A Key Enabler Of 3D NAND
By Laura Peters - 05 Jan, 2026 - Comments: 0

Increased storage needs at the edge and in the cloud are fueling rising demand for higher-capacity flash memory across multiple applications. Released every 12 to 18 months, 3D NAND scaling outpaces most other semiconductor devices in replacement rate and performance gains. With each new generation, NAND suppliers deliver 50% faster read/write speeds, 40% greater bit density, lower latency, ... » read more

Metrology Digs Deep To Produce Next-Generation 3D NAND
By Laura Peters - 09 Dec, 2025 - Comments: 1

Each generation of 3D NAND packs about 30% more bits than the previous version, with current devices storing up to 2 terabits of data in a die the size of a fingernail. With new product introductions shrinking from 18 months to every 12 months, chipmakers are constantly innovating to enable this prodigious scaling pace. 3D NAND technology is a core ingredient in mobile phones, solid-state dr... » read more

Enhancing CMP Process Control with Intelligent Line Monitoring & Integrated Metrology
By Onto Innovation - 09 Dec, 2025 - Comments: 0

New logic transistor designs, 3D NAND stacking, and DRAM integration introduce more CMP layers and tighter process windows. Traditional metrology approaches struggle to keep pace, especially with the need for high sampling rates, multiple control zones, and improved signal-to-noise ratios. Onto Innovation’s Intelligent Line Monitoring & Control with Integrated Metrology offers a new appro... » read more

Scaling Memory With Molybdenum
By Katherine Derbyshire - 18 Sep, 2025 - Comments: 2

Molybdenum is looking increasingly promising as a replacement for a variety of metals commonly used in semiconductor manufacturing today, especially at leading-edge nodes. One by one, chipmakers are crossing metals off the list at advanced nodes. While ruthenium liners are nearly ready for production, the metal is not ready to replace copper in highly scaled interconnects. Ruthenium is very ... » read more

Why 3D NAND Layers Bend (And How To Prevent It)
By Brett Lowe - 21 Aug, 2025 - Comments: 0

3D NAND flash memory is built by vertically stacking multiple alternating layers (tiers) of silicon nitride (SiN) and oxide (TEOS) on top of each other. A major challenge in producing multilayered 3D NAND devices is tier bending and tier collapse. These undesirable conditions can be caused by a combination of factors. Using the virtual Design of Experiment (DOE) capabilities in SEMulator... » read more

Research Bits: July 7
By Jesse Allen - 07 Jul, 2025 - Comments: 0

3D NAND PUF Researchers from Seoul National University developed a new hardware security technology based on commercially available 3D NAND flash memory. The approach is an adaptation of physical unclonable functions (PUFs) with the ability to hide a security key under user data when not in use and reveal it only when needed. The same memory space used for storing security keys can be repurpos... » read more

Interconnects Approach Tipping Point
By Laura Peters - 20 Feb, 2025 - Comments: 0

As leading devices move to next generation nanosheets for logic, their interconnections are getting squeezed past the point where they can deliver low resistance pathways. The 1nm (10Å) node will have 20nm pitch and larger metal lines, but the interconnect stack already consumes a third of device power and accounts for 75% of the chip's RC delay. Changing this dynamic requires a superior co... » read more

Research Bits: Feb. 10
By Jesse Allen - 10 Feb, 2025 - Comments: 0

Speeding up 3D NAND etch Researchers from Lam Research, the University of Colorado Boulder, and Princeton Plasma Physics Laboratory (PPPL) investigated ways to speed up the cryogenic reactive ion etching process for 3D NAND by using a combined hydrogen fluoride gas to create the plasma. “Cryo etch with the hydrogen fluoride plasma showed a significant increase in the etching rate compared... » read more

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