tag: stress

How Multiphysics Is Powering The Future Of 3D-ICs
By John Ferguson - 29 Sep, 2025 - Comments: 0

It’s surprising to learn that the idea of 3D integrated circuits (3D ICs) has been kicking around for over sixty years. Not long after the first MOS IC emerged in 1960, researchers were already thinking vertically. By 1983, Fujitsu manufactured the first 3D IC prototype using through-silicon via (TSV) technology, using laser beam recrystallization. That’s a long time for a good idea to catc... » read more

Data Feed Forward And How It Works: Part 2
By Roberto Colecchia - 09 Sep, 2025 - Comments: 0

As chiplets and advanced packaging redefine semiconductor architecture, managing complexity isn’t just about the silicon—it’s about the data. Modern multi-die packages often contain components from different vendors, integrated in 2.5D or 3D configurations. Each die brings its own risks, and diagnosing issues after assembly is increasingly difficult—especially when data isn’t share... » read more

Electrochemical Absorption of Hydrogen in Structured Palladium Thin-Film Electrodes (Univ. of Bristol)
By Technical Paper Link - 29 Aug, 2025 - Comments: 0

A new technical paper titled "Exploring Electrochemical Methods for Precision Stress Control in Nanoscale Devices " was published by researchers at the University of Bristol. Abstract "Tuning the local film stress (and associated strain) provides a universal route toward exerting dynamic control on propagating fields in nanoscale geometries and engineering controlled interactions between th... » read more

Why 3D NAND Layers Bend (And How To Prevent It)
By Brett Lowe - 21 Aug, 2025 - Comments: 0

3D NAND flash memory is built by vertically stacking multiple alternating layers (tiers) of silicon nitride (SiN) and oxide (TEOS) on top of each other. A major challenge in producing multilayered 3D NAND devices is tier bending and tier collapse. These undesirable conditions can be caused by a combination of factors. Using the virtual Design of Experiment (DOE) capabilities in SEMulator... » read more

Easing The Stress For Package-Level Burn-In
By Laura Peters - 10 Jul, 2025 - Comments: 0

Considered something of a necessary evil, burn-in of IC packages during production does a great job of weeding out latent defects so they don’t turn into failures in the field. But as AI and multi-chiplet packages become more common, and concerns about aging circuitry heighten, shifting stress testing to the wafer level looks increasingly attractive from a quality, throughput, and cost standp... » read more

3D-IC Stress Analysis
By Shetha Nolke - 08 Jul, 2025 - Comments: 0

The semiconductor industry is undergoing a transformation as 3D integrated circuits (ICs) and heterogeneous packaging become mainstream. With these advances comes the promise of higher functional density, a smaller footprint and enhanced system performance. However, these same innovations introduce new mechanical stressors within complex assemblies, posing novel reliability risks across the dev... » read more

Examining Mechanical Deformation In Advanced Logic Devices To Enhance Yield
By Sandy Wen - 19 Jun, 2025 - Comments: 0

By Sandy Wen and Jacky Huang As dimensions shrink and aspect ratios increase in advanced logic devices, it is increasingly important to reduce structural device variation. Structural device variations can be a proxy for device yield. These variations might include critical dimension (CD), gate CD, gate height, and proximity between neighboring vias. One contributor to structural device v... » read more

Challenges With Chiplets And Power Delivery
By Ed Sperling - 15 Apr, 2024 - Comments: 0

Chiplets hold the potential to deliver the same PPA benefits as an SoC, but with many more features and options that are possible on a reticle-constrained die. If chiplets live up to the hype, they will deliver what is essentially mass customization, democratizing and speeding the delivery of complex chips across a broad array of markets. Today, the focus has been on die-to-die interfaces, but ... » read more

How To Plan And Conduct Highly Accelerated Life Testing
By Chris South - 13 Apr, 2023 - Comments: 0

Assessing the robustness of an electronic product is integral to successful design and performance. Highly accelerated life testing (HALT) is an important testing tool for this purpose, and its effectiveness can be maximized through careful planning prior to setup and detailed execution. What is HALT? HALT is the process of applying increased stressors to an electronic device to force failure... » read more

Unknowns Driving Up The Cost Of Auto IC Reliability
By Ed Sperling - 08 Feb, 2022 - Comments: 2

Automotive chipmakers are considering a variety of options to improve the reliability of ICs used for everything from sensors to artificial intelligence. But collectively they could boost the number of process steps, increase the time spent in manufacturing and packaging, and stir up concerns about the amount of data that needs to be collected, shared, and stored. Accounting for advanced pro... » read more

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