Structural Integrity Of Chips

A new challenge is on the horizon, and it’s one that could have some interesting consequences for chip design — structural integrity.

Ever since the introduction of finFETs and 3D NAND, the lines have been blurring between electrical and mechanical engineering. After some initial reports of fins collapsing or breaking, and variable distances between layers, chipmakers figured out how to solve some rather complex structural problems. But as fins become even thinner, eventually replaced by nanosheets, nanowires, and ultimately carbon nanotubes — and as more chips are stacked up either for memory or for complex heterogeneous integration — mechanical engineering will take on a much more significant role in semiconductors.

This already is evident on job boards, where chip companies are advertising for mechanical engineers. Increasingly, chipmakers working on complex designs are building miniature towers, and the more structures they add to a chip, the greater the possibility for mechanical as well as electrical problems. Physical effects in a 3nm stack will be a combination of both, and for each node after that, the two worlds could become almost inseparable.

This has a bearing on the entire design-through-manufacturing flow, which has never really considered such things as stress effects on pillars and microbumps. While it’s well understood, for example, that heat and packaging can put enough strain on a device to warp a multi-chip package or a wafer, that kind of physical stress also has an impact on overall reliability. And as new materials are developed for metal0 and metal1, and as these devices are put together in different ways and expected to function over longer periods of time, stress will play an even greater role.

Nearly all of the development and monitoring tools and tests that exist today focus on electronic functionality. Identifying stress on joints, and watching the impact over time, will require more than just a bunch of sensors scattered around a device. While chips general fail in predictable ways over time, mechanical stresses are less obvious and harder to measure. And while stress points take time to weaken, the actual failures can happen much more quickly. Bridges can collapse within seconds after years of erosion on cables. Steering rods in a car can be working one second and fail the next. And buildings can collapse for a variety of reasons, almost none of which is obvious until the failure actually occurs.

At the single-digit nanometer level, and particularly when multiple chips are sealed in a package, it’s virtually impossible to discern what’s happening without either slicing open a package at the precise point where a failure occurs or using some exotic X-ray technology to take a closer look. And even then, it may be difficult to pinpoint what exactly caused the failure.

Nevertheless, predicting, modeling and detecting those kinds of failures will become essential in the future, particularly as chips find their way into harsh environments such as automobiles, robots, and even communications infrastructure that is exposed to the elements. Also essential will be some way of establishing communication between engineers with expertise in very different areas, something that may seem unnecessary until each begins demanding the same system margin to prevent failures, not to mention the same slice of the corporate budget to make sure these devices will work reliably throughout their expected lifetimes.

The semiconductor industry is itself becoming more complicated and heterogeneous. It now requires multi-physics and cross-domain expertise to build an advanced chip, and that trend will only accelerate and widen as scaling continues and advanced packaging becomes more mainstream. Disciplines that only rarely intersected in the past are suddenly converging at a very high speed, and at this point no one is quite sure how that will play out across the chip industry.