Aging Effects


Tech Talk: Fraunhofer EAS' group manager for quality and reliability, Andre Lange, talks about how to model aging effects and why the problems are becoming more difficult at advanced nodes. https://youtu.be/XHWww2PE7aY » read more

Toward Cross-Layer Resilience


Connected devices are everywhere, and the numbers are growing by orders of magnitude. There are 7 billion people on the planet, but there are expected to be many more billions of connected devices. Each person may have dozens of devices with multiple chips, and those will be connected through infrastructures filled with thousands of additional chips. The problem is that as everything gets c... » read more

Market And Tech Inflections Ahead


Aart de Geus, chairman and co-CEO of Synopsys, sat down with Semiconductor Engineering to talk about the path to autonomous vehicles, industry dis-aggregation and re-aggregation, security issues, and who's going to pay for chips at advanced nodes. SE: All of a sudden we have a bunch of new markets opening up for electronics. We have assisted and autonomous driving, AI and machine learning, v... » read more

Emulation-Driven Implementation


Tech Talk: Haroon Choudry, director of Prime Power at Synopsys, talks about how to shorten time to market and increase confidence in advanced-node designs, while also reducing the amount of guard-banding and improving design freedom. https://youtu.be/xT3CIqjnaBk » read more

Dealing With Resistance In Chips


Chipmakers continue to scale the transistor at advanced nodes, but they are struggling to maintain the same pace with the other two critical parts of the device—the contacts and interconnects. That’s beginning to change, however. In fact, at 10nm/7nm, chipmakers are introducing new topologies and materials such as cobalt, which promises to boost the performance and reduce unwanted resist... » read more

Upcoming System Modeling Challenges


In the past, during the concept phase of a design, system models have typically lacked information regarding reliability. If at all, reliability was addressed late in the design phase shortly before tape out. As the functional safety aspect, and with it an extended device lifetime, gains more and more attention for certain applications, things have to change in the design processes. To ensure a... » read more

Complexity, Reliability And Cost


Peter Schneider, director of Fraunhofer's Engineering of Adaptive Systems Division, sat down with Semiconductor Engineering to talk about future challenges in complexity, time to market and reliability issues, advanced packaging architectures, and the impact of billions of connected devices. What follows are excerpts of that discussion. SE: What is the biggest challenge you see in the semico... » read more

Ensuring Chip Reliability From The Inside


Monitoring activity and traffic is emerging as an essential ingredient in complex, heterogeneous chips used in automotive, industrial, and data center applications. This is particularly true in safety-critical applications such as automotive, where much depends on the system operating exactly right at all times. To make autonomous and assisted driving possible, a mechanism to ensure systems ... » read more

Higher Performance, Lower Power Everywhere


The future of technology is all about information—not just data—at our fingertips, anywhere and at any time. But making all of this work properly will require massive improvements in both performance and power efficiency. There are several distinct pieces to this picture. One is architectural, which is possibly the simplest to understand, the most technologically challenging to realize, ... » read more

Early Chip-Package-System Thermal Analysis


Next-generation automotive, HPC and networking applications are pushing the requirements of thermal integrity and reliability, as they need to operate in extreme conditions for extended periods of time. FinFET designs have high dynamic power density, and power directly impacts the thermal signature of the chip. Thermal degradation typically occurs over an extended period of chip operation. ... » read more

← Older posts