What’s Missing In Test

Experts at the Table: Semiconductor Engineering sat down to discuss how functional test content is brought up at first silicon, and the balance between ATE and system-level testing, with Klaus-Dieter Hilliges, V93000 platform extension manager at Advantest Europe; Robert Cavagnaro, fellow in the Design Engineering Group at Intel (responsible for manufacturing and test strategy of data center... » read more

Automotive Electronics Reliability Requires In-Field Silicon Monitoring

By Lorin Kennedy and Dan Alexandrescu For everyday consumers, no products require reliability more than automobiles. While consumers may be willing accept their laptops and phones limiting performance or abruptly turning off when systems reach unacceptable temperature levels, that is not the case for the reliability of Advanced Driver-Assistance Systems (ADAS) or other safety critical system... » read more

Power-Aware Revolution In Automated Test For ICs

As semiconductor devices advance in complexity and sensitivity to power fluctuations, the integration of power-aware automatic test pattern generation (ATPG) is becoming indispensable for yield and the overall functionality of a chip. Unlike traditional ATPG, which generates test patterns solely to ensure device functionality, power-aware ATPG takes it a step further by meticulously consider... » read more

Making Adaptive Test Work Better

One of the big challenges for IC test is making sense of mountains of data, a direct result of more features being packed onto a single die, or multiple chiplets being assembled into an advanced package. Collecting all that data through various agents and building models on the tester no longer makes sense for a couple reasons — there is too much data, and there are multiple customers using t... » read more

Chip Design Digs Deeper Into AI

Growing demand for blazing fast and extremely dense multi-chiplet systems are pushing chip design deeper into AI, which increasingly is viewed as the best solution for sifting through scores of possible configurations, constraints, and variables in the least amount of time. This shift has broad implications for the future of chip design. In the past, collaborations typically involved the chi... » read more

The Future Of Fault Coverage In Chips

Heterogeneous integration and sophisticated packaging are making chips more difficult to test, necessitating more versatile and efficient testing methods to minimize the time and cost it takes for each test insertion. In the past, test costs typically were limited to about 2% of the total cost of a chip. That cost has been rising in recent years, and with chiplets, advanced packaging, and mo... » read more

Electromigration Concerns Grow In Advanced Packages

The incessant demand for more speed in chips requires forcing more energy through ever-smaller devices, increasing current density and threatening long-term chip reliability. While this problem is well understood, it's becoming more difficult to contain in leading-edge designs. Of particular concern is electromigration, which is becoming more troublesome in advanced packages with multiple ch... » read more

IC Test And Quality Requirements Drive New Collaboration

Rapidly increasing chip and package complexity, coupled with an incessant demand for more reliability, has triggered a frenzy of alliances and working relationships that are starting to redefine how chips are tested and monitored. At the core of this shift is a growing recognition that no company can do everything, and that to work together will require much tighter integration of flows, met... » read more

Early Cycle Analysis And Verification Of Logical SEU Mitigation

The global appetite for data continues to soar, driving innovation across all industry sectors, including how space-based technology can facilitate a more connected world. Miniaturized satellites configured into constellations offer faster communication and higher bandwidth than lone satellites flying higher in geocentric or high-earth orbits. However, industry analysis suggests that to make... » read more

Cost And Quality Of Chiplets

Chiplets add a whole new challenge for the semiconductor industry. How much testing is enough? How do you optimize system binning? What’s the right amount of burn-in? The answers to these questions will vary, depending upon cost and quality tradeoffs, the number and source of the chiplets, and real-world workloads and projected lifespans. Marc Jacobs, senior director of solutions architectur... » read more

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