Power-Aware Revolution In Automated Test For ICs

New approaches can improve yield and reliability, but they add more complexity into the test process.


As semiconductor devices advance in complexity and sensitivity to power fluctuations, the integration of power-aware automatic test pattern generation (ATPG) is becoming indispensable for yield and the overall functionality of a chip.

Unlike traditional ATPG, which generates test patterns solely to ensure device functionality, power-aware ATPG takes it a step further by meticulously considering the power implications of these patterns. This requires sophisticated algorithms and tools capable of analyzing and optimizing power usage during test pattern generation, along with a comprehensive understanding of the power domains within the chip to predict and manage power consumption. Those predictions are sometimes inaccurate and need to be fine-tuned, but the benefits outweigh any drawbacks.

“Customers often run simulations to predict power behavior, but actual results can vary significantly,” says Ed Seng, strategic marketing manager for advanced digital at Teradyne. “The challenge is how to help them process an imperfect simulation without knowing exactly how it’s going to play out once they have real silicon on a tester. They have to adapt.”

Simulations provide a controlled environment to predict power behavior, but actual silicon testing can reveal discrepancies that need to be addressed to refine the simulation models. This feedback loop between simulation and real-world testing is crucial for refining the accuracy of power predictions and ensuring the device performs as expected under different power conditions.

“The primary objective of structural test — which is the ATPG, and scan is a part of it — is to test the device under the same power conditions as the mission-mode operation to minimize the risk of over-testing or under-testing during production,” says Sri Ganta, director of test products at Synopsys. “That includes keeping the test power within the functional mode of the power budget.”

The need for power-aware ATPG
Traditional ATPG methods often fall short in addressing power implications during testing, potentially leading to yield loss and increased test costs. This is largely because these methods do not account for the complex power dynamics that occur during both normal operation and stress conditions. Conventional testing can result in uneven power distribution across the chip, causing local hot spots or voltage droops that compromise the integrity of the device under test.

“Power-aware ATPG is able to construct pattern sets in a way that the power consumption is more homogeneous, making temperature control easier and keeping voltage droops within acceptable limits,” says Frank Mielke, solution architect at Advantest. “Voltage droops can not only lead to yield loss, but also to an increased dppm rate due to missing the appropriate stress conditions, while hot spot temperatures can result in pre-damage, causing yield loss or lower quality.”

Voltage droop, which is a sudden drop in voltage due to high power consumption, can result in timing violations, ultimately leading to functional failures. Conversely, hot spots—a result of concentrated power usage in certain areas—can elevate local temperatures, exacerbating thermal stresses which may pre-damage sensitive regions of the chip. These conditions compromise the reliability and functionality of the device. They can lead to false failures, in which fully functional devices are misclassified as defective, as well as to inadequate stress testing, which allows defective devices to pass.

“If ATPG patterns are not optimized for the device’s power-mesh design, it can lead to unnecessary yield loss due to false failures, potentially discarding good parts and impacting overall costs significantly,” says Synopsys’ Ganta. “The challenge is to optimize these ATPG patterns that strike the right balance between the power budget and the number of patterns. And you need to quickly find that early in the design flow so you can generate more accurate power-aware ATPG patterns that are guaranteed to work in silicon and reduce the number of feedback loops.”

Balancing test power and pattern count
As the threat of causing damage during testing increases, designers must employ strategies for generating test patterns efficiently, providing the necessary test coverage while managing power consumption.

Achieving this balance often involves using low-power design techniques, such as clock gating and power gating, during the test phase. These techniques help to reduce the overall power consumed during testing by shutting down certain sections of the chip that are not under test while maintaining the functionality of the rest of the chip.

“Because the power-net is known, one can create a pattern with the best usage of available power without the need for putting a margin in for unknowns,” says Advantest’s Mielke. “With a good DFT (design for test) implementation, it is also possible to change some parameters, like capture clocks or shift speeds to harmonize power usage during pattern runs, which increases the overall capability and leads to lower pattern counts.”

New ATPG tools can integrate power analysis directly into the ATPG process. These tools can predict power consumption for each test pattern and adjust the patterns accordingly to ensure they stay within certain power limits. This integration allows for tighter control over power usage and makes it easier to identify and correct patterns that might otherwise cause overheating or voltage droop.

“Traditional ATPG tools often use speculative methods to limit the toggle rate, which may not be optimized and can result in inflated pattern counts,” adds Ganta. “Optimizing ATPG patterns based on actual power budgets, rather than speculative toggle rates, can reduce the feedback loops and work faster in silicon.”

Fig. 1: Conventional vs. power-aware ATPG. Source: Synopsys

Scan networks
One of the key advancements addressing this optimization challenge is the adoption of scan networks. By enhancing the traditional scan chain architecture, scan networks enable more flexible and efficient delivery of scan data, thus supporting advanced testing techniques that are crucial for power-aware ATPG.

Scan networks consist of interconnected scan cells that form a network, allowing for more dynamic and adaptable testing strategies. This is especially important for large and complex systems-on-chip (SoCs) and multi-chip modules (MCMs), where traditional testing methods may fall short.

“Technologies like scan networks and high-speed functional interfaces offer new capabilities and flexibilities,” says Teradyne’s Seng. “It changes the game for DFT designers and test engineers because it breaks apart the delivery of the scan data from the external of the device to the circuit or block under test, and this decoupling allows flexibility. They can recreate those test patterns to do more together, or do different things together — all after the silicon is already online, which is really valuable.”

A core advantage of scan networks in power-aware ATPG is their ability to manage power consumption more effectively. By dynamically adjusting the delivery of test data, scan networks help maintain uniform power consumption across the chip, thus preventing voltage droop and hot spots that can lead to functional failures. Additionally, scan networks provide greater flexibility in handling different power domains within a chip. They can adapt to varying power conditions by adjusting the flow of test data, ensuring that all areas of the chip are tested under optimal power conditions. This flexibility is particularly vital for devices with complex power environments, such as AI chips and chiplets.

Scan networks also offer the benefit of post-silicon retargeting. This means that if initial tests reveal power consumption issues or other defects, test patterns can be adjusted and retargeted without the need to redesign the entire test sequence. This adaptability ensures that test procedures remain effective even as device conditions change.

In addition, advanced testing techniques such as adaptive voltage scaling (AVS) and dynamic voltage frequency scaling (DVFS) are enabled by scan networks. AVS involves adjusting the voltage supply to different parts of the chip based on their power needs, and scan networks support AVS by providing precise control over the delivery of test data. Similarly, DVFS adjusts both the voltage and frequency to optimize power usage, and scan networks can dynamically alter the test patterns to align with the changing voltage and frequency requirements, enhancing the efficiency of power-aware ATPG.

Ensuring the compatibility of scan networks with various chip architectures and power domains can be complex. Consequently, integrating scan networks into existing testing infrastructure requires careful planning and coordination between design and test engineering teams.

Advanced packaging considerations
Power-aware ATPG is essential for current semiconductor technologies, but it also plays a critical role in emerging technologies such as AI chips and chiplets. Advanced packaging techniques introduce unique challenges that necessitate a flexible and comprehensive approach to ATPG.

“Especially in this area, we have the core-binning (redundancy/frequency/voltage) and changing power environments,” says Advantest’s Mielke. “Thus, for big clusters like SoCs or MCMs, flexible implementation of power-aware ATPG with the possibility of reordering or changing pattern bursts, and the generation of different pattern sets, will be essential.”

The ability to adapt ATPG patterns based on actual power and thermal measurements ensures that these advanced technologies can be tested accurately and efficiently. This adaptability is crucial, as it allows engineers to account for varying power demands and thermal conditions during different operational states.

Ensuring accurate power performance data in these configurations requires careful consideration of the entire test solution, from design to execution. For instance, chiplets increasingly require heterogeneous integration, where different components with varying power characteristics are integrated into a single package. This integration demands a precise approach to manage power domains and ensure uniform power distribution during testing and usage.

“The heterogeneous integration involved in technologies like AI chips and 3D-ICs influences how we design and sign off on power-aware ATPG patterns,” says Synopsys’ Ganta. “For instance, tile-based and multi-core designs necessitate using test strategies like packetized scan, where patterns are applied through a test bus and time-multiplexed across different cores. Measuring the power at the chip level during such tests presents significant challenges.”

The complexity of testing in advanced packaging also necessitates cross-domain collaboration between design teams and test engineers. Addressing power management issues early in the design phase can significantly improve the efficiency of power-aware ATPG.

“Design and test teams must collaborate closely to implement effective test strategies for low-power devices and advanced packaging,” says Mielke. “This collaboration ensures that design considerations such as power domain partitioning and thermal management are aligned with test requirements.”

Power-aware ATPG and machine learning
Data analysis and machine learning are becoming integral to power-aware ATPG. Leveraging these advanced technologies can significantly improve test efficiency, accuracy, and power management.

“Collecting and analyzing parametric data during testing provides deeper insights into device behavior,” says Seng. “By capturing detailed power consumption data across various operational states, engineers can gain a comprehensive understanding of a device’s power profile and identify patterns and anomalies through big data insights.”

Machine learning algorithms enhance simulations and predictions, making the entire testing process more robust and reliable. They can be employed to predict power consumption trends and identify areas where power can be optimized without compromising test coverage.

“AI and machine learning are instrumental in optimizing ATPG patterns,” adds Ganta. “AI-driven test pace optimization helps tune various parameters, making it possible to handle the exponentially growing pattern counts efficiently.”

Continuous advancements in machine learning and data analytics also play a significant role in enhancing the feedback loop between test simulations and real-world outcomes. By analyzing data from multiple test cycles and different chips, these technologies help in refining ATPG processes, thus improving accuracy and efficiency.

“Data becomes far more important in the training and validating of these algorithms than ever has been in the past,” says Charles Schroeder, an NI fellow. “If you don’t have a sufficient quantity and quality of training data, you’re at a disadvantage and probably can’t do your job. Measurement data becomes very important, not just in the quality of the product end of the line, but in training the algorithm in the design phase.”

For AI chips and chiplets, power consumption significantly influences thermal behavior. Where power demands are highly variable, machine learning can identify the most efficient test patterns that meet power and thermal constraints, predict power consumption in real time, and detect anomalies, providing immediate feedback to the ATPG system.

The need for power-aware ATPG is expected to grow significantly in the coming years. As semiconductor devices continue to evolve, the challenges associated with power management and thermal effects will become increasingly complex.

The integration of AI/ML also plays a transformative role in power-aware ATPG. By analyzing large datasets from multiple test cycles and different chips, machine learning algorithms can identify patterns and anomalies, providing feedback that improves the accuracy and efficiency of ATPG processes. Collaboration between design and test teams can help smooth out any problems here. This includes the application of techniques such as adaptive voltage scaling (AVS) and dynamic voltage frequency scaling (DVFS), which require close coordination to be effective.

Looking forward, the semiconductor industry also needs to address the growing complexity of devices, such as AI chips and chiplets. These technologies involve heterogeneous integration, where different components with varying power characteristics are combined into a single package. Additional future trends include the development of more robust and scalable algorithms that can handle integrated device complexity using more accurate power models. By continuously refining the models with data from actual test runs, engineers can best ensure ATPG pattern effectiveness under all possible conditions.

Related Reading
Testing ICs Faster, Sooner, And Better
Why test cells could become the critical information hub of the fab.
Chiplets: 2023 (EBook)
What chiplets are, what they are being used for today, and what they will be used for in the future.

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