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Power-Aware Test: Addressing Power Challenges In DFT And Test


Integrated circuit (IC) sizes continue to grow as they meet the compute requirements of cutting-edge applications such as artificial intelligence (AI), autonomous driving, and data centers. As design sizes increase, the total power consumption of the chip also increases. While process node scaling reduces a transistor’s size and its operating-voltage, power scaling has not kept up with the si... » read more

Test Becomes Power-Aware


Power-aware test plans are changing, becoming far more extensive than the minimalist plans that were common just a few years ago. In the past would determine if they could power their design up, power it down, then they’d declare it done. “Sometimes they would find they could power it up and power it down once, but they couldn’t power it up a second time because they’d forgotten to ... » read more

Don’t Forget Test


In the modeling of designs for power, engineers make sure to include real system modes and get real activity vectors but, according to Pete Hardee at Cadence, there are a few things they are forgetting. “If the only activity you are using is your simulation test vectors, those are probably pretty unrealistic and that’s a big source of error. One other thing we see—and this is quite imp... » read more