Power-Aware Test: Beyond Low-Power Test

By Rahul Singhal and Likith Kumar Manchukonda

Power consumption is one of the key considerations when designing today’s semiconductor chips and systems. Over the years, the constant need for higher performance and more functions from the chips has been driving the continuous requirement for higher transistor density. The process node scaling makes this possible by reducing transistor sizes and allowing more of them to be packed together in the same die area. Process node scaling reduces the transistor’s size and operating voltage, which helps reduce power. However, the power scaling has not kept up with size scaling and therefore, an increasing transistor density has resulted in increased power density of SoCs as shown in figure 1, and higher overall power consumption. This challenge forces chip designers to use different low-power design techniques to stay within the chip power specifications during the functional mode. Some of the common techniques are gating power domains to turn off inactive blocks to reduce static power, clock-gating to reduce dynamic power consumption and dynamic voltage-frequency scaling.

Fig. 1: Power consumption trend of 80mm² SoC. Source: IRDS 2020 Update, page 16

Challenges with traditional low-power test techniques

Staying within the chip power budget is an even bigger challenge during device tests. This is because the pattern count and test cost are minimized with high fault detection per pattern, but such patterns can result in up to 20x higher peak switching activity and higher peak test power than during functional operation. However, test power exceeding functional power limits can cause false IR-drop failures or permanent damage to the device.

Test engineers add power constraints during pattern generation to mitigate this problem, but it increases the pattern count. Achieving the balance between test power and pattern count requires careful estimation of test power constraints because over-constraining results in pattern inflation and longer automatic test pattern generation (ATPG) time but under-constraining could cause power budget violations.

With simpler low-power chip design techniques in the past, the power consumption typically has been directly proportional to the design’s switching activity and the methodology of applying constraints during ATPG was sufficient to control power and maintain pattern count. In advanced designs with complex power-aware schemes that use standard cells with different operating voltages, the switching activity doesn’t correlate well with power, and the power estimations during ATPG fail to match the actual power characteristics of the design. This results in unreliable constraints during ATPG leading to pattern count inflation and/or test power issues on the tester. Hence the traditional low power ATPG to simply reduce the test power is not enough, and an advanced power-aware ATPG technique is needed that optimizes pattern count and test power together.

Power-aware ATPG with power sign-off data

To address the challenge of poor correlation, Synopsys TestMAX ATPG provides a unique power-aware ATPG solution that leverages power simulation sign-off data from Synopsys PrimePower. The solution uses the average power consumption of combinational, sequential, and memory cells in the design and more accurately models the design’s switching activity and power characteristics. This allows users to determine more accurate switching constraints enabling minimized power-aware pattern count and ATPG runtime while also meeting the power budget on the tester. The following section shows the data and the benefits of PrimePower-based power-aware ATPG capability of Synopsys TestMAX ATPG to addresses both pattern inflation and power budget violation challenges.

Addressing pattern inflation

Fig. 2: Non-linear relationship between switching and power with traditional low-power ATPG due to inaccurate power-to-toggle modeling; causes pattern inflation.

Figure 2 shows a graph on sequential elements switching-activity vs. peak power for all test patterns for an industry design generated using PrimePower [1]. With inaccurate switching activity modeling in traditional low-power ATPG, the power analysis of sample patterns could incorrectly conclude 20,000 (8% of sequential cells) peak switching activity to correspond to 100 watts of peak power limit. During actual ATPG with those constraints, the patterns in the yellow region would be incorrectly discarded because they have higher toggling even though the power budget requirements are met. ATPG would replace these patterns by generating a larger number of new patterns but with less toggling per pattern to keep their switching activity in the green region. This causes unnecessary pattern inflation and adds to ATPG runtime, increasing test costs.

Figure 3 shows the plot using PrimePower based methodology and accounting for combinational cell toggling in addition to sequential cells for the same design. The more accurate modeling provides a linear power-to-switching activity relationship and a more accurate peak switching activity constraint of 168000 corresponding to 100W. This allows ATPG to pack more toggling per pattern while staying within the 100W power budget, which enables higher fault detection per pattern for a lower total pattern count. The normalized data in Table 1 shows that PrimePower based ATPG has a 26% lower pattern count and 19% lower runtime than the traditional low-power ATPG approach even with higher toggling [1].

Fig. 3: PrimePower-based power aware ATPG showing linear relationship between switching and power due to accurate power-to-toggle modeling; generates optimal power-aware patterns.

Table 1: PrimePower based ATPG demonstrated 26% lower pattern count and 19% faster runtime compared to traditional low power ATPG.

Addressing power budget violation

Fig. 4: Power-to-toggle graph for a design showing peak switching of 250 sequential cells corresponds to 0.4125w power.

Figure 4 shows a graph on sequential elements switching-activity vs. peak power for a different design. Based on this graph, a switching activity limit of 25% or 250 sequential cells was chosen corresponding to the power limit of 0.4125 watts, and a complete ATPG pattern set was generated which was analyzed for their peak power consumption using PrimePower. This data for the patterns with power limit is shown in figure 5 below, and it can be noticed that all the patterns had peak switching activity below 250 as expected, but several patterns still violated the power budget of 0.4125 watts. Many patterns between 150 and 200 with similar toggling have large variations in their power consumption. Such behavior makes determining the correct switching constraints very challenging. This is, again, due to the poor switching activity modeling with traditional low-power ATPG methodology.

Fig. 5: Patterns under 25% switching constraints but several 0.4125w power budget violations. Initial test power estimations fail with traditional low-power ATPG.

Figure 6 below shows that after including the power data from PrimePower during ATPG, power consumption has a much more predictable trend with the increase in switching activity. Almost all patterns staying under 25% switching constraints (1200 toggles with combinational switching) and meeting 0.4125w power budget as initial test power estimations. Only very few patterns, << 10%, exceed the power limit as compared to the chart in figure 5. These peak power patterns can be selected for dynamic IR-signoff analysis.

Fig. 6: Both 25% switching constraints and actual 0.4125w power budget met with PrimePower-based ATPG.

In conclusion, the traditional methodology of generating low-power test patterns is no longer sufficient for modern designs with complex power-aware schemes. The inaccurate modeling of the switching activity of the design results in inaccurate power estimations and power constraints during ATPG. This not only causes pattern inflation and runtime issues during ATPG, but it also often results in power budget violations on the tester, needing the time and effort of test engineers to root cause the problem and identify workarounds. All these factors result in higher test costs and lower yields. These challenges are addressed by deploying advanced power-aware ATPG methodology provided by Synopsys TestMAX ATPG that leverages power simulation data from the power sign-off tool, PrimePower, during pattern generation for accurate power or switching activity constraints. In addition to delivering highly efficient power-aware patterns, this methodology has also been shown to reduce the IR-drop and Vmin by up to 40% on complex SoC as described in [1].

References:

[1] K. Abdel-Hafez et al., “Comprehensive Power-Aware ATPG Methodology for Complex Low-Power Designs,” 2022 IEEE International Test Conference (ITC), Anaheim, CA, USA, 2022

Likith Kumar Manchukonda is a senior solutions engineer at Synopsys.