Power-Aware Test: Beyond Low-Power Test

By Rahul Singhal and Likith Kumar Manchukonda Power consumption is one of the key considerations when designing today’s semiconductor chips and systems. Over the years, the constant need for higher performance and more functions from the chips has been driving the continuous requirement for higher transistor density. The process node scaling makes this possible by reducing transistor sizes... » read more

LP Test

By Luke Lang Last month, we discussed testing a portion of a chip at a time to reduce overall power dissipation during test. However, this does not address local power dissipation hotspots that can cause excessive IR drop. These hotspots can occur in regions where many nets are switching at the same time. Typically, a chip’s power grid is designed to meet IR drop specification in the func... » read more

The New Frontier: Low-Power Verification And Test

By Ann Steffora Mutschler By now there’s no argument that verification and test strategies must be considered at the very earliest stages of any design cycle, and when it comes to low-power designs, the advanced techniques used and design complexity make the challenges here even more daunting. Low-power verification and test strategies have been in development for a number of years, and it... » read more