Don’t Forget Test

Power-aware test is becoming much more important, but it’s often an afterthought for chip designers.

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In the modeling of designs for power, engineers make sure to include real system modes and get real activity vectors but, according to Pete Hardee at Cadence, there are a few things they are forgetting.

“If the only activity you are using is your simulation test vectors, those are probably pretty unrealistic and that’s a big source of error. One other thing we see—and this is quite important—people forget about test mode,” he said.

This highlights the importance for all of the tools in the flow to understand the power intent. “They have to understand the power domains and what I’m doing, because in terms of when do you measure a lot of people forget about test mode. Test mode is important for a number of reasons. We’ve actually seen people that have maybe 10X—a full order of magnitude—more dynamic power in test mode than they do in their actual real system operating modes. There have been cases where chips blow up on the tester. What do you do about that? You can make sure that your power supply network and your power switches and everything, your regulators are rated to cope with test mode. Then you are completely over-engineering for normal operating mode, so people are reluctant to do that because it costs more and you’re over-engineering the whole supply.”

Power-aware test is becoming a big deal—actually being able to control the dynamic power as a result of test vectors to make sure those don’t exceed normal operating mode by the degree that would cause a problem on the tester. “There’s a lot of technology going into that because the big thing with manufacturing test of a device is that time on the tester is exceedingly costly. Anything that expands the test time is bad news. If you blindly limit the activity in your test vectors you’re going to end up with a long test time. There’s some really interesting technology that’s been around a couple of years, but when people talk about power it’s often forgotten that you need to really optimize those ATPG vectors so that the dynamic power is not exceeded and it doesn’t unnecessarily expand the tester time,” Hardee said.

Another thing that people often forget is that when looking at all the various system modes, what are the sources of power dissipation in different systems? “It’s easy to measure the SoC or digital subsystem but you might be forgetting that you’ve got all the interfaces—modem, display, keyboard—and those may be on or off in different system modes. If I want to look at total power and my total energy to get the battery drained, then I need to consider not just the digital subsystem but the state of these analog interfaces, modems, display drivers. All of this stuff is necessary because that will give me a very different power dissipation when I’m interacting with the device and I’m typing email and the display is on, when I’m streaming video and watching video vs. just making a voice call.

“Clearly you’ve got to look at the whole system and understand all of those interfaces as well as the chip. As a chip designer, you might be very focused on the chip, while the bigger problems are elsewhere,” he concluded.

~Ann Steffora Mutschler