Using Emulators For Power/Performance Tradeoffs


Emulation is becoming the tool of choice for power and performance tradeoffs, scaling to almost unlimited capacity for complex chips used in data centers, AI/ML systems and smart phones. While emulation has long been viewed as an important but expensive asset for chipmakers trying to verify and debug chips, it is now viewed as an essential component for design optimization and analysis much ... » read more

Power Modeling Standard Released


Power is becoming a more important aspect of semiconductor design, but without an industry standard for power models, adoption is likely to be slow and fragmented. That is why Si2 and the IEEE decided to do something about it. Back in 2014, the IEEE expanded its interest in power standards with the creation of two new groups IEEE P2415 - Standard for Unified Hardware Abstraction and Layer fo... » read more

Baum: Finding SoC Power Flaws


A South Korean startup founded by a Samsung engineer-turned-researcher has created a tool that finds power design flaws early in the SoC design process. The startup, Baum, Inc., launched the second version of its power-modeling solution in June at DAC. The product is a power design-verification tool that uses high-level models to create analyses designed to spot design flaws that could creat... » read more

The Week In Review: Design


M&A MIPS has reportedly been acquired again, this time by AI startup Wave Computing. Wave focuses on data center-based neural network training using its parallel dataflow processing architecture. In March, the company signed on to use 64-bit multi-threaded processor cores from MIPS in future projects. Previously, MIPS was owned by Tallwood Venture Capital, which acquired MIPS from Imaginat... » read more

System-Level Power Modeling Takes Root


Power, heat, and their combined effects on aging and reliability, are becoming increasingly critical variables in the design of chips that will be used across a variety of new and existing markets. As more processing moves to edge, where sensors are generating a tsunami of data, there are a number of factors that need to be considered in designs. On one side, power budgets need to reflect th... » read more

Does Power Verification Work?


Functional verification continues to evolve, but power verification—a somewhat new concern—remains at levels of sophistication reminiscent of functional verification 30 years ago. When will power verification catch up and what must to happen to make it possible? These are questions that the industry is still grappling with, and not everyone believes they require answers. Functional error... » read more

Power Modeling And Analysis


Semiconductor Engineering sat down to discuss power modeling and analysis with [getperson id="11489" p_name="Drew Wingard"], CTO at [getentity id="22605" e_name="Sonics"]; [getperson id="11763" comment="Tobias Bjerregaard"], CEO at [getentity id="22908" e_name="Teklatech"]; Vic Kulkarni, vice president and chief strategy officer at [getentity id="22021" e_name="Ansys"]; Andy Ladd, CEO of Baum; ... » read more

Power Modeling and Analysis


Semiconductor Engineering sat down to discuss power modeling and analysis with [getperson id="11489" p_name="Drew Wingard"], chief technology officer at [getentity id="22605" e_name="Sonics"]; [getperson id="11763" comment="Tobias Bjerregaard"], chief executive officer for [getentity id="22908" e_name="Teklatech"]; Vic Kulkarni, vice president and chief strategy officer at [getentity id="22021"... » read more

Power Modeling And Analysis


Semiconductor Engineering sat down to discuss power modeling and analysis with [getperson id="11489" p_name="Drew Wingard"], chief technology officer at [getentity id="22605" e_name="Sonics"]; [getperson id="11763" comment="Tobias Bjerregaard"], CEO for [getentity id="22908" e_name="Teklatech"]; Vic Kulkarni, vice president and chief strategy officer at [getentity id="22021" e_name="ANSYS"]; An... » read more

Power Challenges At 10nm And Below


Current density is becoming much more problematic at 10nm and beyond, increasing the amount of power management that needs to be incorporated into each chip and boosting both design costs and time to market. Current per unit of area has been rising since 90nm, forcing design teams to leverage a number of power-related strategies such as [getkc id="143" kc_name="dynamic voltage and frequency... » read more

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