Power Modeling And Analysis


Semiconductor Engineering sat down to discuss power modeling and analysis with [getperson id="11489" p_name="Drew Wingard"], CTO at [getentity id="22605" e_name="Sonics"]; [getperson id="11763" comment="Tobias Bjerregaard"], CEO at [getentity id="22908" e_name="Teklatech"]; Vic Kulkarni, vice president and chief strategy officer at [getentity id="22021" e_name="Ansys"]; Andy Ladd, CEO of Baum; ... » read more

Power Modeling and Analysis


Semiconductor Engineering sat down to discuss power modeling and analysis with [getperson id="11489" p_name="Drew Wingard"], chief technology officer at [getentity id="22605" e_name="Sonics"]; [getperson id="11763" comment="Tobias Bjerregaard"], chief executive officer for [getentity id="22908" e_name="Teklatech"]; Vic Kulkarni, vice president and chief strategy officer at [getentity id="22021"... » read more

Power Modeling And Analysis


Semiconductor Engineering sat down to discuss power modeling and analysis with [getperson id="11489" p_name="Drew Wingard"], chief technology officer at [getentity id="22605" e_name="Sonics"]; [getperson id="11763" comment="Tobias Bjerregaard"], CEO for [getentity id="22908" e_name="Teklatech"]; Vic Kulkarni, vice president and chief strategy officer at [getentity id="22021" e_name="ANSYS"]; An... » read more

Power Challenges At 10nm And Below


Current density is becoming much more problematic at 10nm and beyond, increasing the amount of power management that needs to be incorporated into each chip and boosting both design costs and time to market. Current per unit of area has been rising since 90nm, forcing design teams to leverage a number of power-related strategies such as [getkc id="143" kc_name="dynamic voltage and frequency... » read more

Closing The Loop On Power Optimization


[getkc id="108" kc_name="Power"] has become a significant limiter for the capabilities of a chip at finer geometries, and making sure that performance is maximized for a given amount of power is becoming a critical design issue. But that is easier said than done, and the tools and methodologies to overcome the limitations of power are still in the early definition stages. The problem spans a... » read more

Getting The Power/Performance Ratio Right


Getting to market quickly means determining as soon as possible if a concept for a new design will work or not, particularly where power and performance are concerned. Making this determination requires intimate knowledge of the scenarios in which the device will operate — and that is just the start. In order to set things up, you need to somehow model the system, which could be done in a ... » read more

Early Power Modeling Using SystemC And TSMC System-PPA


Power consumption is often more important than performance in today’s SoC designs because of battery size and power dissipation limitations. The dilemma is that the most leverage available to optimize power consumption is at the architectural design stage, but there often is not enough information available early enough to make accurate power decisions. On the performance side, SystemC mod... » read more

Power Options And Issues


In the quest to get SoC power right as early as possible in the design flow, it still holds true that the biggest impact occurs at the beginning of the project, with diminished results as a design progresses through the flow toward tapeout. [getentity id="22186" e_name="ARM's"] big.LITTLE architecture has gained a lot of traction here, prompting MediaTek to introduce its Tri-Gear big.Medium.... » read more

Reaching The Power Budget


Everything related to power in chip design today is a big deal—and it’s just getting bigger. Meeting the power budget is becoming harder at each new node, but it's also becoming difficult in a number of new application areas at existing nodes. That's a big problem because [getkc id="108" kc_name="power"] is now considered a competitive advantage in many markets. It's also one of the most... » read more

2.5D Becomes A Reality


Semiconductor Engineering sat down to discuss 2.5D and advanced packaging with Max Min, senior technical manager at [getentity id="22865" e_name="Samsung"]; Rob Aitken, an [getentity id="22186" comment="ARM"] fellow; John Shin, vice president at [getentity id="22903" e_name="Marvell"]; Bill Isaacson, director of ASIC marketing at [getentity id="22242" e_name="eSilicon"]; Frank Ferro, senior di... » read more

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