Baum: Finding SoC Power Flaws

Identifying power design flaws early with time/power-use analysis.


A South Korean startup founded by a Samsung engineer-turned-researcher has created a tool that finds power design flaws early in the SoC design process.

The startup, Baum, Inc., launched the second version of its power-modeling solution in June at DAC. The product is a power design-verification tool that uses high-level models to create analyses designed to spot design flaws that could create power or thermal issues in low-power, mobile and other power- and heat-sensitive applications, said Andy Ladd, Baum’s CEO (pictured, left).

The basic technology was patented in 2010 by company founder and current COO Joonhwan (Steve) Yi, who was looking for a faster, more complete power analysis tool that could be used earlier in the design process than those he had available as leader of an electronic system level (ESL) design group building SoCs at Samsung Electronics.

“There were tools to do performance analysis, but not for power analysis that would give a good look at the power/performance tradeoff when designing chips,” Ladd said. “He couldn’t get that from another vendor, so he ended up striking out on his own.” Analysis tools available at the time focused on gate-level analysis that came far too late in the process and could examine only one part of a chip at a time—a major drawback at a time when the impact of Moore’s Law weakened and engineers had to add more complexity to an SoC design to create the same impact, Ladd said.

The most reliable models used to result from analysis of old designs, but those don’t accurately reflect advanced-process design and don’t allow scenario-testing of how changing algorithms or workloads affect the power use, and don’t begin to address thermal analysis, which is increasingly important in low-power and IoT design, according to designers quoted in an analysis in Semiconductor Engineering.

Yi (pictured, right) worked on simulation models for Samsung, based partly on his Ph.D. research into high-level analysis of high-density SoC circuits, before leaving to focus more time on research as an assistant professor at Kwangwoon University in Seoul, where he published several papers demonstrating increasing accuracy with models based on synthesis of clock-gating logic.

The company launched in 2016, after winning prizes as “most investable” company in a startup-pitch-off competition run by K-Startup Global Engine, a government-run project that promotes Korean startups. Baum recruited Youngsoo Shin—a professor at Korea Advanced Institute of Science and Technology whose research focuses on high-level power modeling and chip design—as CTO.

The company landed 1.1 billion KRW (about $992,000 USD) in Series A funding from Korea-based K cube Ventures (now Kakao Ventures), which it planned to use to expand its development team and market its flagship PowerBaum to engineering groups building chips aimed at IoT, mobile, multimedia, automotive, networking and server devices.
“We extract the power model from the logic of the design,” Ladd said. “That lets us give users more information on where the problem might be. Rather than just say there is a GPU with a power-idle problem, we can show the clock gating that is relevant to the specific problem.”

PowerBaum is designed to allow power and thermal analysis during the design phase by using netlist and register-transfer level (RTL) data to build a high-performance model representing power flows with near gate-level accuracy that can be set to analyze only the IP from a specific block or can cover the whole chip at once. That allows testing of IP from a single vendor or a whole-chip approach to identify unknown flaws, check timing, identify thermal issues and other analyses, Ladd said.

The high level of abstraction allows greater speed than gate-level analysis, and creates a platform for analysis using a variety of other tools using both dynamic and static power analysis methods.

The model and process to create it has been refined to the point that models are 95% accurate, which is an improvement over gate-level analysis tools that average about 80% accuracy, Ladd said.

The company focused first on development of mobile and IoT chips because power issues are so critical to performance, battery life and even security.

Though not a primary function, it is also possible to use PowerBaum models to identify potential side-channel attacks on the chipsets of IoT devices, many of which are vulnerable to thermal mapping that can identify effective potential points of attack.

Being able to identify and recreate waveforms allows designers to change the logic of a chip enough to conceal its security information to minimize the chance of compromise, Ladd said.

“Traditionally people were only concerned with performance information, not security, but we’re able to run scenarios that allows you to see where the information might be exposed and change the power profile to obfuscate it,” Ladd said.

The company, which introduced version 2.0 of PowerBaum at the Design Automation Conference in June in San Francisco, focused on improved speed and accuracy in the power modeling and analysis, Ladd said.

Noteworthy additions to PowerBaum Version 2.0 include the ability to work effectively with hardware emulators to allow for scenario testing for problems that might crop up only at a certain temperature or processing load or only at a specific point in the cycle. PowerBaum models create time-based power waveforms and integrate effectively with RTL and SystemC simulators, Ladd said.

“You can create the power model and then plug it into another simulator or emulator,” Ladd said. That expands the potential market by making PowerBaum models available to a customer’s existing tools and expands the number and types of specific analysis possible using the same model.

Another big change in V.2 is the ability to run power/performance analyses at different temperatures as well as at different points in the clock cycle.

Mapping time cycles provides a more concrete way to analyze a problem, or at least identify more closely the conditions under which it occurs, Ladd said.

Time cycles can identify problems like a component that goes to idle after consuming the first set of data, but consumes 50% more power after going to idle after the second frame, Ladd said.

“With existing solutions it’s possible to totally miss that problem because you were analyzing the active state and hadn’t thought to look at the idle state,” Ladd said. “That gives designers a better path to fixing the problem.”

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