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Process Corner Explosion


The number of corners that need to be checked is exploding at 7nm and below, fueled by everything from temperature and voltage to changes in metal. Lowering risk and increasing predictability of an SoC at those nodes starts with understanding what will happen when a design is manufactured on a particular foundry process, captured in process corners. This is basically a way of modeling what i... » read more

UPF-Aware Clock-Domain Crossing


Synopsys’ Namit Gupta talks with Semiconductor Engineering about low-power design techniques at the most advanced process nodes, including how to verify the impact of CDC on power at the register transfer level, how to avoid bugs caused by the post-RTL insertion of low-power devices such as isolation, retention and level shifters. https://youtu.be/HwRe9DHLfmg » read more

Baum: Finding SoC Power Flaws


A South Korean startup founded by a Samsung engineer-turned-researcher has created a tool that finds power design flaws early in the SoC design process. The startup, Baum, Inc., launched the second version of its power-modeling solution in June at DAC. The product is a power design-verification tool that uses high-level models to create analyses designed to spot design flaws that could creat... » read more

The Rising Cost Of 5G


Semiconductor Engineering sat down to talk about challenges and progress in 5G with Yorgos Koutsoyannopoulos, president and CEO of Helic; Mike Fitton, senior director of strategic planning and business development at Achronix; Sarah Yost, senior product marketing manager at National Instruments; and Arvind Vel, director of product management at ANSYS. What follows are excerpts of that conversat... » read more

Where FD-SOI Works Best


Semiconductor Engineering sat down to discuss changes in the FD-SOI world and what's behind them, with James Lamb, deputy CTO for advanced semiconductor manufacturing and corporate technical fellow at Brewer Science; Giorgio Cesana, director of technical marketing at STMicroelectronics; Olivier Vatel, senior vice president and CTO at Screen Semiconductor Solutions; and Carlos Mazure, CTO at Soi... » read more

More Performance At The Edge


Shrinking features has been a relatively inexpensive way to improve performance and, at least for the past few decades, to lower power. While device scaling will continue all the way to 3nm and maybe even further, it will happen at a slower pace. Alongside of that scaling, though, there are different approaches on tap to ratchet up performance even with chips developed at older nodes. This i... » read more

Utilizing Clock-Gating Efficiency To Reduce Power In RTL Designs


With the advent of the consumer era and the popularity of mobile applications, power optimization is the mantra of the day. Designers go through several iterations to optimize power in order to achieve their power budgets. The average Clock-Gating Efficiency for a design is a much better indicator of dynamic power consumption because it is a measure of both how many and how long registers are g... » read more

Changing The Design Flow


Synopsys’ Michael Jackson talks with Semiconductor Engineering about why it’s becoming necessary to fuse together various pieces of digital design. https://youtu.be/AOWh4wjw-ps » read more

High-Speed SerDes At 7nm


eSilicon’s David Axelrad discusses the challenges with 56Gbps and 112Gps SerDes, and why the switch from analog to digital is required for performance and low power. https://youtu.be/E-CU8TLvjjc » read more

New Roadmap For Electronics


Tech Talk: Melissa Grupen-Shemansky, CTO for SEMI’s FlexTech Group and Advanced Packaging program, looks at what’s changing now that Moore’s Law is slowing, and how packaging is changing as the traditional physical boundaries of electronics begin breaking down. https://youtu.be/UpH1m8Oru90 » read more

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