Partitioning Drives Architectural Considerations


There are multiple reasons for design partitioning. One is complexity, because it’s faster and simpler to divide and conquer, particularly with third-party IP. A second reason involves power, where it may be more efficient to divide up functionality so each function be right-sized. A third involves performance, where memory utilization and processing can be split up according to functional pr... » read more

Baum: Finding SoC Power Flaws


A South Korean startup founded by a Samsung engineer-turned-researcher has created a tool that finds power design flaws early in the SoC design process. The startup, Baum, Inc., launched the second version of its power-modeling solution in June at DAC. The product is a power design-verification tool that uses high-level models to create analyses designed to spot design flaws that could creat... » read more

The Week In Review: Design


M&A MIPS has reportedly been acquired again, this time by AI startup Wave Computing. Wave focuses on data center-based neural network training using its parallel dataflow processing architecture. In March, the company signed on to use 64-bit multi-threaded processor cores from MIPS in future projects. Previously, MIPS was owned by Tallwood Venture Capital, which acquired MIPS from Imaginat... » read more

Chip Dis-Integration


Just because something can be done does not always mean that it should be done. One segment of the semiconductor industry is learning the hard way that continued chip integration has a significant downside. At the same time, another another group has just started to see the benefits of consolidating functionality onto a single substrate. Companies that have been following Moore's Law and hav... » read more

The Week In Review: Design


M&A Imagination will sell its MIPS business to Tallwood, a California-based venture capital firm, for $65m in cash. The sale is expected to close in October. The rest of Imagination is slated to be sold to Canyon Bridge for £550 million in cash (~$740 million), a deal dependent on the MIPS sale. The Chinese-backed investment firm has featured recently in the news for its attempted purchas... » read more

Power Modeling And Analysis


Semiconductor Engineering sat down to discuss power modeling and analysis with [getperson id="11489" p_name="Drew Wingard"], CTO at [getentity id="22605" e_name="Sonics"]; [getperson id="11763" comment="Tobias Bjerregaard"], CEO at [getentity id="22908" e_name="Teklatech"]; Vic Kulkarni, vice president and chief strategy officer at [getentity id="22021" e_name="Ansys"]; Andy Ladd, CEO of Baum; ... » read more

Power Modeling and Analysis


Semiconductor Engineering sat down to discuss power modeling and analysis with [getperson id="11489" p_name="Drew Wingard"], chief technology officer at [getentity id="22605" e_name="Sonics"]; [getperson id="11763" comment="Tobias Bjerregaard"], chief executive officer for [getentity id="22908" e_name="Teklatech"]; Vic Kulkarni, vice president and chief strategy officer at [getentity id="22021"... » read more

Dealing With System-Level Power


Analyzing and managing power at the system level is becoming more difficult and more important—and slow to catch on. There are several reasons for this. First, design automation tools have lagged behind an understanding of what needs to be done. Second, modeling languages and standards are still in flux, and what exists today is considered inadequate. And third, while system-level power ha... » read more

The Week In Review: Design


Tools Mentor added new tools to its high-level synthesis portfolio. The DesignChecks tool helps find bugs during coding with a static mode that performs very fast linting-like checks of the code and a formal mode that uses a formal engine for a more exhaustive proof of issues. The synthesis-aware Coverage tool measures code coverage for C++ signoff and fast closure of synthesized RTL. It sup... » read more

Transient Power Problems Rising


Transient power is becoming much more problematic at 10/7nm, adding yet another level of complexity for design teams already wrestling with power issues caused by leakage, a variety of power management techniques to control dynamic power, and leakage current. At each new node there is less headroom for engineering teams to address these problems, and more likelihood that what they do in one ... » read more